Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA
Modeling and simulation/emulation play a major role in research and development of novel Networks-on-Chip (NoCs). However, conventional software simulators are so slow that studying NoCs for emerging many-core systems with hundreds to thousands of cores is challenging. State-of-the-art FPGA-based No...
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Veröffentlicht in: | ACM transactions on reconfigurable technology and systems 2017-12, Vol.10 (4), p.1-27 |
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description | Modeling and simulation/emulation play a major role in research and development of novel Networks-on-Chip (NoCs). However, conventional software simulators are so slow that studying NoCs for emerging many-core systems with hundreds to thousands of cores is challenging. State-of-the-art FPGA-based NoC emulators have shown great potential in speeding up the NoC simulation, but they cannot emulate large-scale NoCs due to the FPGA capacity constraints. Moreover, emulating large-scale NoCs under synthetic workloads on FPGAs typically requires a large amount of memory and thus involves the use of off-chip memory, which makes the overall design much more complicated and may substantially degrade the emulation speed. This article presents methods for fast and cycle-accurate emulation of NoCs with up to thousands of nodes using a single FPGA. We first describe how to emulate a NoC under a synthetic workload using only FPGA on-chip memory (BRAMs). We next present a novel use of time-division multiplexing where BRAMs are effectively used for emulating a network using a small number of nodes, thereby overcoming the FPGA capacity constraints. We propose methods for emulating both direct and indirect networks, focusing on the commonly used meshes and fat-trees (
k
-ary
n
-trees). This is different from prior work that considers only direct networks. Using the proposed methods, we build a NoC emulator, called FNoC, and demonstrate the emulation of some mesh-based and fat-tree-based NoCs with canonical router architectures. Our evaluation results show that (1) the size of the largest NoC that can be emulated depends on only the FPGA on-chip memory capacity; (2) a mesh-based NoC with 16,384 nodes (128×128 NoC) and a fat-tree-based NoC with 6,144 switch nodes and 4,096 terminal nodes (4-ary 6-tree NoC) can be emulated using a single Virtex-7 FPGA; and (3) when emulating these two NoCs, we achieve, respectively, 5,047× and 232× speedups over BookSim, one of the most widely used software-based NoC simulators, while maintaining the same level of accuracy. |
doi_str_mv | 10.1145/3151758 |
format | Article |
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k
-ary
n
-trees). This is different from prior work that considers only direct networks. Using the proposed methods, we build a NoC emulator, called FNoC, and demonstrate the emulation of some mesh-based and fat-tree-based NoCs with canonical router architectures. Our evaluation results show that (1) the size of the largest NoC that can be emulated depends on only the FPGA on-chip memory capacity; (2) a mesh-based NoC with 16,384 nodes (128×128 NoC) and a fat-tree-based NoC with 6,144 switch nodes and 4,096 terminal nodes (4-ary 6-tree NoC) can be emulated using a single Virtex-7 FPGA; and (3) when emulating these two NoCs, we achieve, respectively, 5,047× and 232× speedups over BookSim, one of the most widely used software-based NoC simulators, while maintaining the same level of accuracy.</description><identifier>ISSN: 1936-7406</identifier><identifier>EISSN: 1936-7414</identifier><identifier>DOI: 10.1145/3151758</identifier><language>eng</language><ispartof>ACM transactions on reconfigurable technology and systems, 2017-12, Vol.10 (4), p.1-27</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-a0a24f69893d521d0c07d7f41e7755924a065bc08f7efe9f37f82d3862e12f5f3</citedby><cites>FETCH-LOGICAL-c291t-a0a24f69893d521d0c07d7f41e7755924a065bc08f7efe9f37f82d3862e12f5f3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Chu, Thiem Van</creatorcontrib><creatorcontrib>Sato, Shimpei</creatorcontrib><creatorcontrib>Kise, Kenji</creatorcontrib><title>Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA</title><title>ACM transactions on reconfigurable technology and systems</title><description>Modeling and simulation/emulation play a major role in research and development of novel Networks-on-Chip (NoCs). However, conventional software simulators are so slow that studying NoCs for emerging many-core systems with hundreds to thousands of cores is challenging. State-of-the-art FPGA-based NoC emulators have shown great potential in speeding up the NoC simulation, but they cannot emulate large-scale NoCs due to the FPGA capacity constraints. Moreover, emulating large-scale NoCs under synthetic workloads on FPGAs typically requires a large amount of memory and thus involves the use of off-chip memory, which makes the overall design much more complicated and may substantially degrade the emulation speed. This article presents methods for fast and cycle-accurate emulation of NoCs with up to thousands of nodes using a single FPGA. We first describe how to emulate a NoC under a synthetic workload using only FPGA on-chip memory (BRAMs). We next present a novel use of time-division multiplexing where BRAMs are effectively used for emulating a network using a small number of nodes, thereby overcoming the FPGA capacity constraints. We propose methods for emulating both direct and indirect networks, focusing on the commonly used meshes and fat-trees (
k
-ary
n
-trees). This is different from prior work that considers only direct networks. Using the proposed methods, we build a NoC emulator, called FNoC, and demonstrate the emulation of some mesh-based and fat-tree-based NoCs with canonical router architectures. Our evaluation results show that (1) the size of the largest NoC that can be emulated depends on only the FPGA on-chip memory capacity; (2) a mesh-based NoC with 16,384 nodes (128×128 NoC) and a fat-tree-based NoC with 6,144 switch nodes and 4,096 terminal nodes (4-ary 6-tree NoC) can be emulated using a single Virtex-7 FPGA; and (3) when emulating these two NoCs, we achieve, respectively, 5,047× and 232× speedups over BookSim, one of the most widely used software-based NoC simulators, while maintaining the same level of accuracy.</description><issn>1936-7406</issn><issn>1936-7414</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><recordid>eNo9kF1LwzAYhYMoOKf4F3LnVTRvvnNZyjaFosLcdYlpMqtdO5IO2b-34vDqOXDgHHgQugV6DyDkAwcJWpozNAPLFdECxPl_puoSXeX8SaniyogZ2ixdHrHrG1wefRdI4f0huTHgxe7QubEdejxEXLm0DWTtXRfwcxi_h_SVydCT8qPd401u-y12eD1h6pevq-IaXUTX5XBz4nz6WbyVj6R6WT2VRUU8szASRx0TUVljeSMZNNRT3egoIGgtpWXCUSXfPTVRhxhs5Doa1nCjWAAWZeRzdPe369OQcwqx3qd259KxBlr_2qhPNvgPKyxPlw</recordid><startdate>20171201</startdate><enddate>20171201</enddate><creator>Chu, Thiem Van</creator><creator>Sato, Shimpei</creator><creator>Kise, Kenji</creator><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20171201</creationdate><title>Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA</title><author>Chu, Thiem Van ; Sato, Shimpei ; Kise, Kenji</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-a0a24f69893d521d0c07d7f41e7755924a065bc08f7efe9f37f82d3862e12f5f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chu, Thiem Van</creatorcontrib><creatorcontrib>Sato, Shimpei</creatorcontrib><creatorcontrib>Kise, Kenji</creatorcontrib><collection>CrossRef</collection><jtitle>ACM transactions on reconfigurable technology and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chu, Thiem Van</au><au>Sato, Shimpei</au><au>Kise, Kenji</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA</atitle><jtitle>ACM transactions on reconfigurable technology and systems</jtitle><date>2017-12-01</date><risdate>2017</risdate><volume>10</volume><issue>4</issue><spage>1</spage><epage>27</epage><pages>1-27</pages><issn>1936-7406</issn><eissn>1936-7414</eissn><abstract>Modeling and simulation/emulation play a major role in research and development of novel Networks-on-Chip (NoCs). However, conventional software simulators are so slow that studying NoCs for emerging many-core systems with hundreds to thousands of cores is challenging. State-of-the-art FPGA-based NoC emulators have shown great potential in speeding up the NoC simulation, but they cannot emulate large-scale NoCs due to the FPGA capacity constraints. Moreover, emulating large-scale NoCs under synthetic workloads on FPGAs typically requires a large amount of memory and thus involves the use of off-chip memory, which makes the overall design much more complicated and may substantially degrade the emulation speed. This article presents methods for fast and cycle-accurate emulation of NoCs with up to thousands of nodes using a single FPGA. We first describe how to emulate a NoC under a synthetic workload using only FPGA on-chip memory (BRAMs). We next present a novel use of time-division multiplexing where BRAMs are effectively used for emulating a network using a small number of nodes, thereby overcoming the FPGA capacity constraints. We propose methods for emulating both direct and indirect networks, focusing on the commonly used meshes and fat-trees (
k
-ary
n
-trees). This is different from prior work that considers only direct networks. Using the proposed methods, we build a NoC emulator, called FNoC, and demonstrate the emulation of some mesh-based and fat-tree-based NoCs with canonical router architectures. Our evaluation results show that (1) the size of the largest NoC that can be emulated depends on only the FPGA on-chip memory capacity; (2) a mesh-based NoC with 16,384 nodes (128×128 NoC) and a fat-tree-based NoC with 6,144 switch nodes and 4,096 terminal nodes (4-ary 6-tree NoC) can be emulated using a single Virtex-7 FPGA; and (3) when emulating these two NoCs, we achieve, respectively, 5,047× and 232× speedups over BookSim, one of the most widely used software-based NoC simulators, while maintaining the same level of accuracy.</abstract><doi>10.1145/3151758</doi><tpages>27</tpages></addata></record> |
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title | Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA |
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