Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization

This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus on control-flow intensive descriptions, characterized b...

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Veröffentlicht in:	ACM transactions on design automation of electronic systems 1998-04, Vol.3 (2), p.285-307
Hauptverfasser:	Bhattacharya, Subhrajit, Dey, Sujit, Breglez, Franc
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit optimization Datapath optimization Electronic design automation Hardware High-level and register-transfer level synthesis Logic synthesis
Online-Zugang:	Volltext
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