Application of Extreme Ultraviolet Lithography to Test Chip Fabrication

Extreme ultraviolet (EUV) lithography is considered to be the most promising technology for meeting the lithographic challenges posed by the next generation semiconductor design rule beyond a half pitch (hp) of 22 nm. A key area of the Selete EUV program is proof of manufacturability, which means ve...

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Veröffentlicht in:Japanese Journal of Applied Physics 2011-06, Vol.50 (6), p.06GB08-06GB08-5
Hauptverfasser: Tawarayama, Kazuo, Nakajima, Yumi, Kyoh, Suigen, Aoyama, Hajime, Matsunaga, Kentaro, Tanaka, Satoshi, Magoshi, Shunko
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container_end_page 06GB08-5
container_issue 6
container_start_page 06GB08
container_title Japanese Journal of Applied Physics
container_volume 50
creator Tawarayama, Kazuo
Nakajima, Yumi
Kyoh, Suigen
Aoyama, Hajime
Matsunaga, Kentaro
Tanaka, Satoshi
Magoshi, Shunko
description Extreme ultraviolet (EUV) lithography is considered to be the most promising technology for meeting the lithographic challenges posed by the next generation semiconductor design rule beyond a half pitch (hp) of 22 nm. A key area of the Selete EUV program is proof of manufacturability, which means verification of module integration for EUV lithography. To accomplish this, many technologies [e.g., mask, exposure tool, resist, optical proximity correction (OPC)] need to be developed and integrated. In this paper, we discuss the current status of each of them. To verify EUV's manufacturability, we applied EUV to test chip fabrication, metal wiring fabrication, and electrical measurement. The yield number of the hp 28 nm pattern is 70% after improving the resist and the etching process. These results show demonstrate that EUV lithography is a practical technology that is now suitable for semiconductor devices for $2x$ nm area.
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fullrecord <record><control><sourceid>ipap_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1143_JJAP_50_06GB08</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>10_1143_JJAP_50_06GB08</sourcerecordid><originalsourceid>FETCH-LOGICAL-c295t-a0711996d31688bc6e0d45fbfaf6e6ca4632cef1bdc5b1965ff8c3a5f6bef2b43</originalsourceid><addsrcrecordid>eNqFkEFPwyAAhYnRxDq9euZs0goUWHusy1ZdmuhhOxOgYDGdEEqM-_du6e6eXl7yvnf4AHjEqMCYls_bbfNRMFQg3r6g6gpkuKTLnCLOrkGGEME5rQm5BXfT9HWqnFGcgbYJYXRaJue_obdw_ZuiORi4H1OUP86PJsHOpcF_RhmGI0we7syU4GpwAW6kihf2HtxYOU7m4ZILsN-sd6vXvHtv31ZNl2tSs5RLtMS4rnlfYl5VSnODesqsstJyw7WkvCTaWKx6zRSuObO20qVklitjiaLlAhTzr45-mqKxIkR3kPEoMBJnDeKsQTAkZg0n4GkGXJDhv_Efi7VexA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Application of Extreme Ultraviolet Lithography to Test Chip Fabrication</title><source>IOP Publishing Journals</source><source>Institute of Physics (IOP) Journals - HEAL-Link</source><creator>Tawarayama, Kazuo ; Nakajima, Yumi ; Kyoh, Suigen ; Aoyama, Hajime ; Matsunaga, Kentaro ; Tanaka, Satoshi ; Magoshi, Shunko</creator><creatorcontrib>Tawarayama, Kazuo ; Nakajima, Yumi ; Kyoh, Suigen ; Aoyama, Hajime ; Matsunaga, Kentaro ; Tanaka, Satoshi ; Magoshi, Shunko</creatorcontrib><description>Extreme ultraviolet (EUV) lithography is considered to be the most promising technology for meeting the lithographic challenges posed by the next generation semiconductor design rule beyond a half pitch (hp) of 22 nm. A key area of the Selete EUV program is proof of manufacturability, which means verification of module integration for EUV lithography. To accomplish this, many technologies [e.g., mask, exposure tool, resist, optical proximity correction (OPC)] need to be developed and integrated. In this paper, we discuss the current status of each of them. To verify EUV's manufacturability, we applied EUV to test chip fabrication, metal wiring fabrication, and electrical measurement. The yield number of the hp 28 nm pattern is 70% after improving the resist and the etching process. These results show demonstrate that EUV lithography is a practical technology that is now suitable for semiconductor devices for $2x$ nm area.</description><identifier>ISSN: 0021-4922</identifier><identifier>EISSN: 1347-4065</identifier><identifier>DOI: 10.1143/JJAP.50.06GB08</identifier><language>eng</language><publisher>The Japan Society of Applied Physics</publisher><ispartof>Japanese Journal of Applied Physics, 2011-06, Vol.50 (6), p.06GB08-06GB08-5</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c295t-a0711996d31688bc6e0d45fbfaf6e6ca4632cef1bdc5b1965ff8c3a5f6bef2b43</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Tawarayama, Kazuo</creatorcontrib><creatorcontrib>Nakajima, Yumi</creatorcontrib><creatorcontrib>Kyoh, Suigen</creatorcontrib><creatorcontrib>Aoyama, Hajime</creatorcontrib><creatorcontrib>Matsunaga, Kentaro</creatorcontrib><creatorcontrib>Tanaka, Satoshi</creatorcontrib><creatorcontrib>Magoshi, Shunko</creatorcontrib><title>Application of Extreme Ultraviolet Lithography to Test Chip Fabrication</title><title>Japanese Journal of Applied Physics</title><description>Extreme ultraviolet (EUV) lithography is considered to be the most promising technology for meeting the lithographic challenges posed by the next generation semiconductor design rule beyond a half pitch (hp) of 22 nm. A key area of the Selete EUV program is proof of manufacturability, which means verification of module integration for EUV lithography. To accomplish this, many technologies [e.g., mask, exposure tool, resist, optical proximity correction (OPC)] need to be developed and integrated. In this paper, we discuss the current status of each of them. To verify EUV's manufacturability, we applied EUV to test chip fabrication, metal wiring fabrication, and electrical measurement. The yield number of the hp 28 nm pattern is 70% after improving the resist and the etching process. These results show demonstrate that EUV lithography is a practical technology that is now suitable for semiconductor devices for $2x$ nm area.</description><issn>0021-4922</issn><issn>1347-4065</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><recordid>eNqFkEFPwyAAhYnRxDq9euZs0goUWHusy1ZdmuhhOxOgYDGdEEqM-_du6e6eXl7yvnf4AHjEqMCYls_bbfNRMFQg3r6g6gpkuKTLnCLOrkGGEME5rQm5BXfT9HWqnFGcgbYJYXRaJue_obdw_ZuiORi4H1OUP86PJsHOpcF_RhmGI0we7syU4GpwAW6kihf2HtxYOU7m4ZILsN-sd6vXvHtv31ZNl2tSs5RLtMS4rnlfYl5VSnODesqsstJyw7WkvCTaWKx6zRSuObO20qVklitjiaLlAhTzr45-mqKxIkR3kPEoMBJnDeKsQTAkZg0n4GkGXJDhv_Efi7VexA</recordid><startdate>20110601</startdate><enddate>20110601</enddate><creator>Tawarayama, Kazuo</creator><creator>Nakajima, Yumi</creator><creator>Kyoh, Suigen</creator><creator>Aoyama, Hajime</creator><creator>Matsunaga, Kentaro</creator><creator>Tanaka, Satoshi</creator><creator>Magoshi, Shunko</creator><general>The Japan Society of Applied Physics</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20110601</creationdate><title>Application of Extreme Ultraviolet Lithography to Test Chip Fabrication</title><author>Tawarayama, Kazuo ; Nakajima, Yumi ; Kyoh, Suigen ; Aoyama, Hajime ; Matsunaga, Kentaro ; Tanaka, Satoshi ; Magoshi, Shunko</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c295t-a0711996d31688bc6e0d45fbfaf6e6ca4632cef1bdc5b1965ff8c3a5f6bef2b43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tawarayama, Kazuo</creatorcontrib><creatorcontrib>Nakajima, Yumi</creatorcontrib><creatorcontrib>Kyoh, Suigen</creatorcontrib><creatorcontrib>Aoyama, Hajime</creatorcontrib><creatorcontrib>Matsunaga, Kentaro</creatorcontrib><creatorcontrib>Tanaka, Satoshi</creatorcontrib><creatorcontrib>Magoshi, Shunko</creatorcontrib><collection>CrossRef</collection><jtitle>Japanese Journal of Applied Physics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Tawarayama, Kazuo</au><au>Nakajima, Yumi</au><au>Kyoh, Suigen</au><au>Aoyama, Hajime</au><au>Matsunaga, Kentaro</au><au>Tanaka, Satoshi</au><au>Magoshi, Shunko</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Application of Extreme Ultraviolet Lithography to Test Chip Fabrication</atitle><jtitle>Japanese Journal of Applied Physics</jtitle><date>2011-06-01</date><risdate>2011</risdate><volume>50</volume><issue>6</issue><spage>06GB08</spage><epage>06GB08-5</epage><pages>06GB08-06GB08-5</pages><issn>0021-4922</issn><eissn>1347-4065</eissn><abstract>Extreme ultraviolet (EUV) lithography is considered to be the most promising technology for meeting the lithographic challenges posed by the next generation semiconductor design rule beyond a half pitch (hp) of 22 nm. A key area of the Selete EUV program is proof of manufacturability, which means verification of module integration for EUV lithography. To accomplish this, many technologies [e.g., mask, exposure tool, resist, optical proximity correction (OPC)] need to be developed and integrated. In this paper, we discuss the current status of each of them. To verify EUV's manufacturability, we applied EUV to test chip fabrication, metal wiring fabrication, and electrical measurement. The yield number of the hp 28 nm pattern is 70% after improving the resist and the etching process. These results show demonstrate that EUV lithography is a practical technology that is now suitable for semiconductor devices for $2x$ nm area.</abstract><pub>The Japan Society of Applied Physics</pub><doi>10.1143/JJAP.50.06GB08</doi></addata></record>
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title Application of Extreme Ultraviolet Lithography to Test Chip Fabrication
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T10%3A51%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ipap_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Application%20of%20Extreme%20Ultraviolet%20Lithography%20to%20Test%20Chip%20Fabrication&rft.jtitle=Japanese%20Journal%20of%20Applied%20Physics&rft.au=Tawarayama,%20Kazuo&rft.date=2011-06-01&rft.volume=50&rft.issue=6&rft.spage=06GB08&rft.epage=06GB08-5&rft.pages=06GB08-06GB08-5&rft.issn=0021-4922&rft.eissn=1347-4065&rft_id=info:doi/10.1143/JJAP.50.06GB08&rft_dat=%3Cipap_cross%3E10_1143_JJAP_50_06GB08%3C/ipap_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true