Merged DRAM with Logic/Analog (MDLA) Technology for Single-Chip Solution

This paper describes a process integration of M erged D RAM (dynamic random access memory) with L ogic and A nalog (MDLA) using high performance 0.35 µm CMOS technology for the implementation of “System on a Chip”. DRAM whose cell size was 2.1 µm 2 and analog cores were embedded in 0.35 µm logic chi...

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Veröffentlicht in:	Japanese Journal of Applied Physics 1999-04, Vol.38 (4S), p.2183
Hauptverfasser:	Yoon, Jong Shik, Yu, Sunil, Lee, Hyae Ryoung, Kwon, Chul-Soon, Kim, Dong Woo, Kim, Won Chul, Choi, Chang-Sik
Format:	Artikel
Sprache:	eng
Online-Zugang:	Volltext
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