Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications

Transistor sizing and spacing are constantly decreasing due to the continuous advancement of CMOS technology. The charge of the sensitive nodes in the static random access memory (SRAM) cell gradually decreases, making the SRAM cell more and more sensitive to soft errors, such as single-node upsets...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2024-10, p.1-13
Hauptverfasser:	Cai, Shuo, Liang, Xinjie, Huang, Zhu, Wang, Weizheng, Yu, Fei
Format:	Artikel
Sprache:	eng
Schlagworte:	Double-node upsets (DNUs) Feedback loop high-speed Integrated circuit reliability low-power Power demand Reliability self-recovery SRAM cells Stacking static random access memory (SRAM) Transforms Transistors Very large scale integration Voltage
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