An Area-Efficient, Conflict-Free, and Configurable Architecture for Accelerating NTT/INTT

The Number Theoretic Transform (NTT) is a widely adopted method for accelerating polynomial multiplication in lattice-based cryptosystems. Consequently, numerous hardware accelerators have been developed to enhance the speed of the NTT algorithm. Area-Time Product (ATP) and configurability are criti...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2024-03, Vol.32 (3), p.519-529
Hauptverfasser:	Liu, Si-Huang, Kuo, Chia-Yi, Mo, Yan-Nan, Su, Tao
Format:	Artikel
Sprache:	eng
Schlagworte:	Accelerators Algorithms Clocks Computer architecture Computer systems Configurable architecture for accelerating number theoretic transform (NTT)/inverse NTT (INTT) conflict-free memory access pattern Cryptography Efficiency Hardware lattice-based cryptosystems Lattices NTT Parallel processing Parameters polynomial multiplier Polynomials Random access memory Transforms Very large scale integration
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