Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT

With the relentless scaling of technology nodes, design technology co-optimization (DTCO) for the conventional (Conv.) cell structure is starting to reach its limitations due to limited routing resources, lateral p-n separations, and performance requirements. As a result, system technology co-optimi...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2021-06, Vol.29 (6), p.1178-1191
Hauptverfasser:	Cheng, Chung-Kuan, Ho, Chia-Tung, Lee, Daeyeal, Lin, Bill, Park, Dongwon
Format:	Artikel
Sprache:	eng
Schlagworte:	Area Automated cell generation cell synthesis complementary-FET (CFET) Computer architecture Design optimization design technology co-optimization (DTCO) Field effect transistors Layout Microprocessors Optimization Pins placement Routing satisfiability modulo theory (SMT) Scaling Separation Shape standard cell Synthesis system technology co-optimization (STCO)
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