Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations
This paper demonstrates autotuning of the coefficients of the feedback loop of an inductive integrated voltage regulator (IVR) using an on-chip delay sensor. The proposed approach improves the effective performance of the digital core under variations in the on-die/package integrated passives and tr...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2019-08, Vol.27 (8), p.1768-1778 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1778 |
|---|---|
| container_issue | 8 |
| container_start_page | 1768 |
| container_title | IEEE transactions on very large scale integration (VLSI) systems |
| container_volume | 27 |
| creator | Chekuri, Venkata Chaitanya Krishna Kar, Monodeep Singh, Arvind Mukhopadhyay, Saibal |
| description | This paper demonstrates autotuning of the coefficients of the feedback loop of an inductive integrated voltage regulator (IVR) using an on-chip delay sensor. The proposed approach improves the effective performance of the digital core under variations in the on-die/package integrated passives and transistor process. A 130-nm CMOS test-chip is designed containing a multisampled 125-MHz IVR with a wirebond inductor, on-die capacitor, and all-digital proportional-integral-differential (PID) controller powering a parallel Advanced Encryption Standard (AES) engine. The autotuning is performed using a Vernier delay line based on-chip delay sensor and an all-digital tuning engine. The measurement results demonstrate up to 5.2% improvement in the maximum operating frequency of the AES core using performance-based autotuning. |
| doi_str_mv | 10.1109/TVLSI.2019.2912141 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TVLSI_2019_2912141</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8718532</ieee_id><sourcerecordid>2264437776</sourcerecordid><originalsourceid>FETCH-LOGICAL-c295t-414b9e8e445648ab4d77bfb2dca8ae143333100a7ddb00aed0e91fc6236dd0bb3</originalsourceid><addsrcrecordid>eNo9UNtKAzEUXETBWv0BfQn4vDXJZi95LPVWKLTYy2vIbs7WLWtSk6xQv95sW5yXGTgzc2Ci6J7gESGYP602s-V0RDHhI8oJJYxcRAOSpnnMAy6DxlkSF5Tg6-jGuR3GhDGOB9HvuPPGd7rRW2RqNNUetlZ6UEGqrvLND6CNab3cAvqAbddKbyxau94_1_Hks9mjZ2jlAS1Bu3DyBq1MC30HWlhTgXNIaoUW0rljmbSN9I3R7ja6qmXr4O7Mw2j9-rKavMez-dt0Mp7FFeWpjxlhJYcCGEszVsiSqTwv65KqShYSCEsCCMYyV6oMBAoDJ3WV0SRTCpdlMoweT717a747cF7sTGd1eCkozRhL8jzPgoueXJU1zlmoxd42X9IeBMGi31gcNxb9xuK8cQg9nEINAPwHipwUaUKTP19lek4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2264437776</pqid></control><display><type>article</type><title>Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations</title><source>IEEE Electronic Library (IEL)</source><creator>Chekuri, Venkata Chaitanya Krishna ; Kar, Monodeep ; Singh, Arvind ; Mukhopadhyay, Saibal</creator><creatorcontrib>Chekuri, Venkata Chaitanya Krishna ; Kar, Monodeep ; Singh, Arvind ; Mukhopadhyay, Saibal</creatorcontrib><description>This paper demonstrates autotuning of the coefficients of the feedback loop of an inductive integrated voltage regulator (IVR) using an on-chip delay sensor. The proposed approach improves the effective performance of the digital core under variations in the on-die/package integrated passives and transistor process. A 130-nm CMOS test-chip is designed containing a multisampled 125-MHz IVR with a wirebond inductor, on-die capacitor, and all-digital proportional-integral-differential (PID) controller powering a parallel Advanced Encryption Standard (AES) engine. The autotuning is performed using a Vernier delay line based on-chip delay sensor and an all-digital tuning engine. The measurement results demonstrate up to 5.2% improvement in the maximum operating frequency of the AES core using performance-based autotuning.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2019.2912141</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Auto tuning ; CMOS ; Control theory ; Delay lines ; delay-based tuning ; Delays ; dynamic voltage frequency scaling (DVFS) ; Encryption ; Engines ; Feedback loops ; IVR ; performance-based tuning ; Proportional integral derivative ; Regulators ; Sensors ; System-on-chip ; Transient analysis ; Tuning ; Vernier delay chains ; Voltage ; Voltage control ; Voltage regulators</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2019-08, Vol.27 (8), p.1768-1778</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c295t-414b9e8e445648ab4d77bfb2dca8ae143333100a7ddb00aed0e91fc6236dd0bb3</citedby><cites>FETCH-LOGICAL-c295t-414b9e8e445648ab4d77bfb2dca8ae143333100a7ddb00aed0e91fc6236dd0bb3</cites><orcidid>0000-0002-3175-3350 ; 0000-0001-5238-7196</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8718532$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8718532$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chekuri, Venkata Chaitanya Krishna</creatorcontrib><creatorcontrib>Kar, Monodeep</creatorcontrib><creatorcontrib>Singh, Arvind</creatorcontrib><creatorcontrib>Mukhopadhyay, Saibal</creatorcontrib><title>Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>This paper demonstrates autotuning of the coefficients of the feedback loop of an inductive integrated voltage regulator (IVR) using an on-chip delay sensor. The proposed approach improves the effective performance of the digital core under variations in the on-die/package integrated passives and transistor process. A 130-nm CMOS test-chip is designed containing a multisampled 125-MHz IVR with a wirebond inductor, on-die capacitor, and all-digital proportional-integral-differential (PID) controller powering a parallel Advanced Encryption Standard (AES) engine. The autotuning is performed using a Vernier delay line based on-chip delay sensor and an all-digital tuning engine. The measurement results demonstrate up to 5.2% improvement in the maximum operating frequency of the AES core using performance-based autotuning.</description><subject>Auto tuning</subject><subject>CMOS</subject><subject>Control theory</subject><subject>Delay lines</subject><subject>delay-based tuning</subject><subject>Delays</subject><subject>dynamic voltage frequency scaling (DVFS)</subject><subject>Encryption</subject><subject>Engines</subject><subject>Feedback loops</subject><subject>IVR</subject><subject>performance-based tuning</subject><subject>Proportional integral derivative</subject><subject>Regulators</subject><subject>Sensors</subject><subject>System-on-chip</subject><subject>Transient analysis</subject><subject>Tuning</subject><subject>Vernier delay chains</subject><subject>Voltage</subject><subject>Voltage control</subject><subject>Voltage regulators</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9UNtKAzEUXETBWv0BfQn4vDXJZi95LPVWKLTYy2vIbs7WLWtSk6xQv95sW5yXGTgzc2Ci6J7gESGYP602s-V0RDHhI8oJJYxcRAOSpnnMAy6DxlkSF5Tg6-jGuR3GhDGOB9HvuPPGd7rRW2RqNNUetlZ6UEGqrvLND6CNab3cAvqAbddKbyxau94_1_Hks9mjZ2jlAS1Bu3DyBq1MC30HWlhTgXNIaoUW0rljmbSN9I3R7ja6qmXr4O7Mw2j9-rKavMez-dt0Mp7FFeWpjxlhJYcCGEszVsiSqTwv65KqShYSCEsCCMYyV6oMBAoDJ3WV0SRTCpdlMoweT717a747cF7sTGd1eCkozRhL8jzPgoueXJU1zlmoxd42X9IeBMGi31gcNxb9xuK8cQg9nEINAPwHipwUaUKTP19lek4</recordid><startdate>20190801</startdate><enddate>20190801</enddate><creator>Chekuri, Venkata Chaitanya Krishna</creator><creator>Kar, Monodeep</creator><creator>Singh, Arvind</creator><creator>Mukhopadhyay, Saibal</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-3175-3350</orcidid><orcidid>https://orcid.org/0000-0001-5238-7196</orcidid></search><sort><creationdate>20190801</creationdate><title>Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations</title><author>Chekuri, Venkata Chaitanya Krishna ; Kar, Monodeep ; Singh, Arvind ; Mukhopadhyay, Saibal</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c295t-414b9e8e445648ab4d77bfb2dca8ae143333100a7ddb00aed0e91fc6236dd0bb3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Auto tuning</topic><topic>CMOS</topic><topic>Control theory</topic><topic>Delay lines</topic><topic>delay-based tuning</topic><topic>Delays</topic><topic>dynamic voltage frequency scaling (DVFS)</topic><topic>Encryption</topic><topic>Engines</topic><topic>Feedback loops</topic><topic>IVR</topic><topic>performance-based tuning</topic><topic>Proportional integral derivative</topic><topic>Regulators</topic><topic>Sensors</topic><topic>System-on-chip</topic><topic>Transient analysis</topic><topic>Tuning</topic><topic>Vernier delay chains</topic><topic>Voltage</topic><topic>Voltage control</topic><topic>Voltage regulators</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chekuri, Venkata Chaitanya Krishna</creatorcontrib><creatorcontrib>Kar, Monodeep</creatorcontrib><creatorcontrib>Singh, Arvind</creatorcontrib><creatorcontrib>Mukhopadhyay, Saibal</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chekuri, Venkata Chaitanya Krishna</au><au>Kar, Monodeep</au><au>Singh, Arvind</au><au>Mukhopadhyay, Saibal</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2019-08-01</date><risdate>2019</risdate><volume>27</volume><issue>8</issue><spage>1768</spage><epage>1778</epage><pages>1768-1778</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>This paper demonstrates autotuning of the coefficients of the feedback loop of an inductive integrated voltage regulator (IVR) using an on-chip delay sensor. The proposed approach improves the effective performance of the digital core under variations in the on-die/package integrated passives and transistor process. A 130-nm CMOS test-chip is designed containing a multisampled 125-MHz IVR with a wirebond inductor, on-die capacitor, and all-digital proportional-integral-differential (PID) controller powering a parallel Advanced Encryption Standard (AES) engine. The autotuning is performed using a Vernier delay line based on-chip delay sensor and an all-digital tuning engine. The measurement results demonstrate up to 5.2% improvement in the maximum operating frequency of the AES core using performance-based autotuning.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2019.2912141</doi><tpages>11</tpages><orcidid>https://orcid.org/0000-0002-3175-3350</orcidid><orcidid>https://orcid.org/0000-0001-5238-7196</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2019-08, Vol.27 (8), p.1768-1778 |
| issn | 1063-8210 1557-9999 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_TVLSI_2019_2912141 |
| source | IEEE Electronic Library (IEL) |
| subjects | Auto tuning CMOS Control theory Delay lines delay-based tuning Delays dynamic voltage frequency scaling (DVFS) Encryption Engines Feedback loops IVR performance-based tuning Proportional integral derivative Regulators Sensors System-on-chip Transient analysis Tuning Vernier delay chains Voltage Voltage control Voltage regulators |
| title | Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T13%3A59%3A34IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Autotuning%20of%20Integrated%20Inductive%20Voltage%20Regulator%20Using%20On-Chip%20Delay%20Sensor%20to%20Tolerate%20Process%20and%20Passive%20Variations&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Chekuri,%20Venkata%20Chaitanya%20Krishna&rft.date=2019-08-01&rft.volume=27&rft.issue=8&rft.spage=1768&rft.epage=1778&rft.pages=1768-1778&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2019.2912141&rft_dat=%3Cproquest_RIE%3E2264437776%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2264437776&rft_id=info:pmid/&rft_ieee_id=8718532&rfr_iscdi=true |