Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic

High-performance, low-power-consumption, and high-accuracy analog-to-digital converters (ADCs) with a compact area are necessary for a wide range of current applications. This paper presents a pipeline ADC architecture with a novel 3-D clock distribution network utilizing through-silicon via-induced...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2018-12, Vol.26 (12), p.2619-2627
Hauptverfasser:	Mirzaie, Nahid, Alzahmi, Ahmed, Shamsi, Hossein, Byun, Gyung-Su
Format:	Artikel
Sprache:	eng
Schlagworte:	3-D integrated circuits (ICs) Analog to digital conversion Analog to digital converters clock distribution network (CDN) Clocks CMOS data converter Design optimization Distribution management Energy conversion efficiency Error correction evolutionary algorithm Integrated circuits Interconnections Jitter memristor ratioed logic (MRL) Memristors Optimization Optimization techniques performance optimization pipeline analog-to-digital converter (ADC) Pipeline design Pipelines Power consumption Power demand through-silicon via (TSV) Through-silicon vias
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