Array Termination Impacts in Advanced SRAM
An essential goal of the static random access memory (SRAM) array termination design is to both terminate as well as maintain a homogeneous environment for the active edge cells in the array. Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM dev...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2017-09, Vol.25 (9), p.2449-2457 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Mann, Randy W. Puri, Sandeep Sheng Xie Marienfeld, Daniel Versaggi, Joseph Bianzhu Fu Gribelyuk, Michael Thankalekshmi, Ratheesh R. Xiaoqiang Zhang Hui Zang Weintraub, Chad E. |
| description | An essential goal of the static random access memory (SRAM) array termination design is to both terminate as well as maintain a homogeneous environment for the active edge cells in the array. Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM devices in close proximity to the termination region, which can lead to undesirable inhomogenuities in the array. The impact of LLEs, originating from the array termination design, on SRAM read performance and V min fail count, are examined using a 14nm FinFET technology. Large-scale SRAM read performance statistics are analyzed to identify elevated read currents and low-voltage fail counts associated with the array termination. The root cause and modulating factors are explored, and potential solution paths are discussed. |
| doi_str_mv | 10.1109/TVLSI.2017.2713124 |
| format | Article |
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Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM devices in close proximity to the termination region, which can lead to undesirable inhomogenuities in the array. The impact of LLEs, originating from the array termination design, on SRAM read performance and V min fail count, are examined using a 14nm FinFET technology. Large-scale SRAM read performance statistics are analyzed to identify elevated read currents and low-voltage fail counts associated with the array termination. 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Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM devices in close proximity to the termination region, which can lead to undesirable inhomogenuities in the array. The impact of LLEs, originating from the array termination design, on SRAM read performance and V min fail count, are examined using a 14nm FinFET technology. Large-scale SRAM read performance statistics are analyzed to identify elevated read currents and low-voltage fail counts associated with the array termination. The root cause and modulating factors are explored, and potential solution paths are discussed.</description><subject>Arrays</subject><subject>Bit cell</subject><subject>Current measurement</subject><subject>Layout</subject><subject>local layout effect (LLE)</subject><subject>Logic gates</subject><subject>Random access memory</subject><subject>static noise margin (SNM)</subject><subject>static random access memory (SRAM)</subject><subject>statistics</subject><subject>Stress</subject><subject>Systematics</subject><subject>technology scaling</subject><subject>variation</subject><subject>write margin</subject><subject>yield</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9j0tLw0AUhQdRsFb_gG6yFhLvnUemswzFRyAi2Oh2uMlMIGLSMhOE_ntTWzybczbfgY-xW4QMEcxD_VltyowD6oxrFMjlGVugUjo1c87nDblIVxzhkl3F-AWAUhpYsPsiBNontQ9DP9LUb8ekHHbUTjHpx6RwPzS23iWb9-L1ml109B39zamX7OPpsV6_pNXbc7kuqrTluZ5S4h0CkUPjvHYyFwAcFfhGqhU2jchBd8YL5xrBpVGiQ952lDvniTuuSCwZP_62YRtj8J3dhX6gsLcI9mBr_2ztwdaebGfo7gj13vt_QBtlELT4Bfn0UAQ</recordid><startdate>201709</startdate><enddate>201709</enddate><creator>Mann, Randy W.</creator><creator>Puri, Sandeep</creator><creator>Sheng Xie</creator><creator>Marienfeld, Daniel</creator><creator>Versaggi, Joseph</creator><creator>Bianzhu Fu</creator><creator>Gribelyuk, Michael</creator><creator>Thankalekshmi, Ratheesh R.</creator><creator>Xiaoqiang Zhang</creator><creator>Hui Zang</creator><creator>Weintraub, Chad E.</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0001-8373-2052</orcidid></search><sort><creationdate>201709</creationdate><title>Array Termination Impacts in Advanced SRAM</title><author>Mann, Randy W. ; Puri, Sandeep ; Sheng Xie ; Marienfeld, Daniel ; Versaggi, Joseph ; Bianzhu Fu ; Gribelyuk, Michael ; Thankalekshmi, Ratheesh R. ; Xiaoqiang Zhang ; Hui Zang ; Weintraub, Chad E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c267t-a2f10aad19de7d463002150eb4581bb3607f9e3ddb324953f12cfa6ddea2d25a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Arrays</topic><topic>Bit cell</topic><topic>Current measurement</topic><topic>Layout</topic><topic>local layout effect (LLE)</topic><topic>Logic gates</topic><topic>Random access memory</topic><topic>static noise margin (SNM)</topic><topic>static random access memory (SRAM)</topic><topic>statistics</topic><topic>Stress</topic><topic>Systematics</topic><topic>technology scaling</topic><topic>variation</topic><topic>write margin</topic><topic>yield</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Mann, Randy W.</creatorcontrib><creatorcontrib>Puri, Sandeep</creatorcontrib><creatorcontrib>Sheng Xie</creatorcontrib><creatorcontrib>Marienfeld, Daniel</creatorcontrib><creatorcontrib>Versaggi, Joseph</creatorcontrib><creatorcontrib>Bianzhu Fu</creatorcontrib><creatorcontrib>Gribelyuk, Michael</creatorcontrib><creatorcontrib>Thankalekshmi, Ratheesh R.</creatorcontrib><creatorcontrib>Xiaoqiang Zhang</creatorcontrib><creatorcontrib>Hui Zang</creatorcontrib><creatorcontrib>Weintraub, Chad E.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mann, Randy W.</au><au>Puri, Sandeep</au><au>Sheng Xie</au><au>Marienfeld, Daniel</au><au>Versaggi, Joseph</au><au>Bianzhu Fu</au><au>Gribelyuk, Michael</au><au>Thankalekshmi, Ratheesh R.</au><au>Xiaoqiang Zhang</au><au>Hui Zang</au><au>Weintraub, Chad E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Array Termination Impacts in Advanced SRAM</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2017-09</date><risdate>2017</risdate><volume>25</volume><issue>9</issue><spage>2449</spage><epage>2457</epage><pages>2449-2457</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>An essential goal of the static random access memory (SRAM) array termination design is to both terminate as well as maintain a homogeneous environment for the active edge cells in the array. Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM devices in close proximity to the termination region, which can lead to undesirable inhomogenuities in the array. The impact of LLEs, originating from the array termination design, on SRAM read performance and V min fail count, are examined using a 14nm FinFET technology. Large-scale SRAM read performance statistics are analyzed to identify elevated read currents and low-voltage fail counts associated with the array termination. The root cause and modulating factors are explored, and potential solution paths are discussed.</abstract><pub>IEEE</pub><doi>10.1109/TVLSI.2017.2713124</doi><tpages>9</tpages><orcidid>https://orcid.org/0000-0001-8373-2052</orcidid></addata></record> |
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| subjects | Arrays Bit cell Current measurement Layout local layout effect (LLE) Logic gates Random access memory static noise margin (SNM) static random access memory (SRAM) statistics Stress Systematics technology scaling variation write margin yield |
| title | Array Termination Impacts in Advanced SRAM |
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