A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measure...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2016-05, Vol.24 (5), p.1975-1983
Hauptverfasser:	Raja, Immanuel, Banerjee, Gaurab, Zeidan, Mohamad A., Abraham, Jacob A.
Format:	Artikel
Sprache:	eng
Schlagworte:	50% duty cycle Bandwidth Clocks CMOS CMOS integrated circuits correction loop duty-cycle correction (DCC) duty-cycle measurements frequency domain measurements Frequency measurement Harmonic analysis rise/fall time measurements Voltage control
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