Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Henc...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2015-06, Vol.23 (6), p.1180-1184
Hauptverfasser: Narayanamoorthy, Srinivasan, Moghaddam, Hadi Asghari, Zhenhong Liu, Taejoon Park, Nam Sung Kim
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container_title IEEE transactions on very large scale integration (VLSI) systems
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creator Narayanamoorthy, Srinivasan
Moghaddam, Hadi Asghari
Zhenhong Liu
Taejoon Park
Nam Sung Kim
description The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical. In this brief, we propose multiplier architectures that can tradeoff computational accuracy with energy consumption at design time. Compared with a precise multiplier, the proposed multiplier can consume 58% less energy/op with average computational error of \sim 1 %. Finally, we demonstrate that such a small computational error does not notably impact the quality of DSP and the accuracy of classification applications.
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subjects Accuracy
Algorithm design and analysis
Approximation
Digital signal processing
Energy consumption
energy efficiency
Image recognition
Multiplexing
multiplication
Very large scale integration
title Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications
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