Eleven Ways to Boost Your Synchronizer
Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to...
Gespeichert in:
Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2015-06, Vol.23 (6), p.1040-1049 |
---|---|
Hauptverfasser: | , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 1049 |
---|---|
container_issue | 6 |
container_start_page | 1040 |
container_title | IEEE transactions on very large scale integration (VLSI) systems |
container_volume | 23 |
creator | Beer, Salomon Ginosar, Ran |
description | Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimumV TH , overprovisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle. |
doi_str_mv | 10.1109/TVLSI.2014.2331331 |
format | Article |
fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TVLSI_2014_2331331</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6851932</ieee_id><sourcerecordid>10_1109_TVLSI_2014_2331331</sourcerecordid><originalsourceid>FETCH-LOGICAL-c370t-5e384c6d686404bbc9500f9c0506b16a9a5195ac3e38790d88b3c100f3f54cbc3</originalsourceid><addsrcrecordid>eNo9j01LAzEQhoMoWKt_QC978rbrzOZjk6OWVgsLHloVTyGbZnGlbiRZhfXXm9riMDBzeN4ZHkIuEQpEUDfr53q1LEpAVpSUYuojMkHOq1ylOk47CJrLEuGUnMX4DolkCibker51367PXswYs8Fnd97HIXv1XyFbjb19C77vflw4Jyet2UZ3cZhT8rSYr2cPef14v5zd1rmlFQw5d1QyKzZCCgasaaziAK2ywEE0KIwyHBU3liauUrCRsqEWE0Jbzmxj6ZSU-7s2-BiDa_Vn6D5MGDWC3pnqP1O9M9UH0xS62oc659x_QMj0i5b0F4AETkk</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Eleven Ways to Boost Your Synchronizer</title><source>IEEE Electronic Library (IEL)</source><creator>Beer, Salomon ; Ginosar, Ran</creator><creatorcontrib>Beer, Salomon ; Ginosar, Ran</creatorcontrib><description>Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimumV TH , overprovisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2014.2331331</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Clocks ; Latches ; Libraries ; Logic gates ; Metastability ; MTBF ; multistage synchronizers ; Synchronization ; synchronizer ; tau effective ; Transistors</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2015-06, Vol.23 (6), p.1040-1049</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c370t-5e384c6d686404bbc9500f9c0506b16a9a5195ac3e38790d88b3c100f3f54cbc3</citedby><cites>FETCH-LOGICAL-c370t-5e384c6d686404bbc9500f9c0506b16a9a5195ac3e38790d88b3c100f3f54cbc3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6851932$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54737</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6851932$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Beer, Salomon</creatorcontrib><creatorcontrib>Ginosar, Ran</creatorcontrib><title>Eleven Ways to Boost Your Synchronizer</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimumV TH , overprovisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle.</description><subject>Capacitance</subject><subject>Clocks</subject><subject>Latches</subject><subject>Libraries</subject><subject>Logic gates</subject><subject>Metastability</subject><subject>MTBF</subject><subject>multistage synchronizers</subject><subject>Synchronization</subject><subject>synchronizer</subject><subject>tau effective</subject><subject>Transistors</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9j01LAzEQhoMoWKt_QC978rbrzOZjk6OWVgsLHloVTyGbZnGlbiRZhfXXm9riMDBzeN4ZHkIuEQpEUDfr53q1LEpAVpSUYuojMkHOq1ylOk47CJrLEuGUnMX4DolkCibker51367PXswYs8Fnd97HIXv1XyFbjb19C77vflw4Jyet2UZ3cZhT8rSYr2cPef14v5zd1rmlFQw5d1QyKzZCCgasaaziAK2ywEE0KIwyHBU3liauUrCRsqEWE0Jbzmxj6ZSU-7s2-BiDa_Vn6D5MGDWC3pnqP1O9M9UH0xS62oc659x_QMj0i5b0F4AETkk</recordid><startdate>20150601</startdate><enddate>20150601</enddate><creator>Beer, Salomon</creator><creator>Ginosar, Ran</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20150601</creationdate><title>Eleven Ways to Boost Your Synchronizer</title><author>Beer, Salomon ; Ginosar, Ran</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c370t-5e384c6d686404bbc9500f9c0506b16a9a5195ac3e38790d88b3c100f3f54cbc3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2015</creationdate><topic>Capacitance</topic><topic>Clocks</topic><topic>Latches</topic><topic>Libraries</topic><topic>Logic gates</topic><topic>Metastability</topic><topic>MTBF</topic><topic>multistage synchronizers</topic><topic>Synchronization</topic><topic>synchronizer</topic><topic>tau effective</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Beer, Salomon</creatorcontrib><creatorcontrib>Ginosar, Ran</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Beer, Salomon</au><au>Ginosar, Ran</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Eleven Ways to Boost Your Synchronizer</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2015-06-01</date><risdate>2015</risdate><volume>23</volume><issue>6</issue><spage>1040</spage><epage>1049</epage><pages>1040-1049</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimumV TH , overprovisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle.</abstract><pub>IEEE</pub><doi>10.1109/TVLSI.2014.2331331</doi><tpages>10</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 1063-8210 |
ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2015-06, Vol.23 (6), p.1040-1049 |
issn | 1063-8210 1557-9999 |
language | eng |
recordid | cdi_crossref_primary_10_1109_TVLSI_2014_2331331 |
source | IEEE Electronic Library (IEL) |
subjects | Capacitance Clocks Latches Libraries Logic gates Metastability MTBF multistage synchronizers Synchronization synchronizer tau effective Transistors |
title | Eleven Ways to Boost Your Synchronizer |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T10%3A10%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Eleven%20Ways%20to%20Boost%20Your%20Synchronizer&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Beer,%20Salomon&rft.date=2015-06-01&rft.volume=23&rft.issue=6&rft.spage=1040&rft.epage=1049&rft.pages=1040-1049&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2014.2331331&rft_dat=%3Ccrossref_RIE%3E10_1109_TVLSI_2014_2331331%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6851932&rfr_iscdi=true |