Quaternary Logic Lookup Table in Standard CMOS

Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interc...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2015-02, Vol.23 (2), p.306-316
Hauptverfasser:	Brito, Diogo, Rabuske, Taimur G., Fernandes, Jorge R., Flores, Paulo, Monteiro, Jose
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitance CMOS integrated circuits Energy consumption Field-programmable gate array (FPGA) Logic gates lookup table (LUT) multiple-valued logic (MVL) Multiplexing quaternary logic Semiconductors standard CMOS technology Switches Table lookup Transistors
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