On the Design of RNS Reverse Converters for the Four-Moduli Set +1, 2^-1, 2^, 2^+1}+1
In this brief, we propose a method to design efficient adder-based converters for the four-moduli set {2 n +1, 2 n -1, 2 n , 2 n+1 +1} with n odd, which provides a dynamic range of 4n+1 bits for the residue number system (RNS). This method hierarchically applies the mixed radix approach to balanced...
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Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2013-10, Vol.21 (10), p.1945-1949 |
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container_issue | 10 |
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container_title | IEEE transactions on very large scale integration (VLSI) systems |
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creator | Sousa, Leonel Antao, Samuel Chaves, Ricardo |
description | In this brief, we propose a method to design efficient adder-based converters for the four-moduli set {2 n +1, 2 n -1, 2 n , 2 n+1 +1} with n odd, which provides a dynamic range of 4n+1 bits for the residue number system (RNS). This method hierarchically applies the mixed radix approach to balanced pairs of residues in two levels. With the proposed method, only simple binary and modulo 2 k -1 additions are required, fully avoiding the usage of modulo 2 k +1 arithmetic operations, which is a significant advantage over the currently available RNS reverse converters for this type of moduli set. Experimental results show that the delay of the proposed converters is significantly reduced when compared with the related state of the art; for example, for a 65-nm CMOS ASIC technology and a dynamic range of 21 bits, the conversion time and the circuit area are reduced by about 44% and 30%, respectively, while the conversion time is reduced by 34% for a dynamic range of 37 bits with the circuit area increasing only by 25%. Moreover, the proposed reverse converters outperform the related state of the art for any value of n by up to 70%, according to the figure-of-merit energy per conversion. |
doi_str_mv | 10.1109/TVLSI.2012.2219564 |
format | Article |
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This method hierarchically applies the mixed radix approach to balanced pairs of residues in two levels. With the proposed method, only simple binary and modulo 2 k -1 additions are required, fully avoiding the usage of modulo 2 k +1 arithmetic operations, which is a significant advantage over the currently available RNS reverse converters for this type of moduli set. Experimental results show that the delay of the proposed converters is significantly reduced when compared with the related state of the art; for example, for a 65-nm CMOS ASIC technology and a dynamic range of 21 bits, the conversion time and the circuit area are reduced by about 44% and 30%, respectively, while the conversion time is reduced by 34% for a dynamic range of 37 bits with the circuit area increasing only by 25%. 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This method hierarchically applies the mixed radix approach to balanced pairs of residues in two levels. With the proposed method, only simple binary and modulo 2 k -1 additions are required, fully avoiding the usage of modulo 2 k +1 arithmetic operations, which is a significant advantage over the currently available RNS reverse converters for this type of moduli set. Experimental results show that the delay of the proposed converters is significantly reduced when compared with the related state of the art; for example, for a 65-nm CMOS ASIC technology and a dynamic range of 21 bits, the conversion time and the circuit area are reduced by about 44% and 30%, respectively, while the conversion time is reduced by 34% for a dynamic range of 37 bits with the circuit area increasing only by 25%. Moreover, the proposed reverse converters outperform the related state of the art for any value of n by up to 70%, according to the figure-of-merit energy per conversion.</description><subject>Adders</subject><subject>Application specific integrated circuits</subject><subject>Application-specific integrated circuit (ASIC)</subject><subject>Delay</subject><subject>digital hardware design</subject><subject>Dynamic range</subject><subject>Field programmable gate arrays</subject><subject>field-programmable gate array (FPGA)</subject><subject>Hardware</subject><subject>residue number system (RNS)</subject><subject>reverse conversion</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtOw0AMRUcIJErhB2Az-zLF9jySWaJCoVKhUh8siULiQBA0aKZFYsG_kz6EJdt34XtlHSHOEfqI4K_mT-PZqE-A1CdCb505EB20NlG-rcNWg9MqJYRjcRLjOwAa46EjFpOlXL2xvOFYvy5lU8np40xO-ZtDZDlolq1YtVpWTdgeDpt1UA9Nuf6o5YxXsoeXkp7Vdm66h789PBVHVf4R-Wy_u2IxvJ0P7tV4cjcaXI9VgUhGJUVKubPaW6PRQokvRQoMjiBxidXagfPtyzn7tNKVRSxLkxAVZUIuLQunu4J2uUVoYgxcZV-h_szDT4aQbcBkWzDZBky2B9OaLnammpn_DU5b8troP2UjWdA</recordid><startdate>201310</startdate><enddate>201310</enddate><creator>Sousa, Leonel</creator><creator>Antao, Samuel</creator><creator>Chaves, Ricardo</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>201310</creationdate><title>On the Design of RNS Reverse Converters for the Four-Moduli Set +1, 2^-1, 2^, 2^+1}+1</title><author>Sousa, Leonel ; Antao, Samuel ; Chaves, Ricardo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1124-7c82a6539543150d1bc80e06207675336069210ae98f3f511dd4722cd7268dc63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Adders</topic><topic>Application specific integrated circuits</topic><topic>Application-specific integrated circuit (ASIC)</topic><topic>Delay</topic><topic>digital hardware design</topic><topic>Dynamic range</topic><topic>Field programmable gate arrays</topic><topic>field-programmable gate array (FPGA)</topic><topic>Hardware</topic><topic>residue number system (RNS)</topic><topic>reverse conversion</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Sousa, Leonel</creatorcontrib><creatorcontrib>Antao, Samuel</creatorcontrib><creatorcontrib>Chaves, Ricardo</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sousa, Leonel</au><au>Antao, Samuel</au><au>Chaves, Ricardo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>On the Design of RNS Reverse Converters for the Four-Moduli Set +1, 2^-1, 2^, 2^+1}+1</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2013-10</date><risdate>2013</risdate><volume>21</volume><issue>10</issue><spage>1945</spage><epage>1949</epage><pages>1945-1949</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>In this brief, we propose a method to design efficient adder-based converters for the four-moduli set {2 n +1, 2 n -1, 2 n , 2 n+1 +1} with n odd, which provides a dynamic range of 4n+1 bits for the residue number system (RNS). This method hierarchically applies the mixed radix approach to balanced pairs of residues in two levels. With the proposed method, only simple binary and modulo 2 k -1 additions are required, fully avoiding the usage of modulo 2 k +1 arithmetic operations, which is a significant advantage over the currently available RNS reverse converters for this type of moduli set. Experimental results show that the delay of the proposed converters is significantly reduced when compared with the related state of the art; for example, for a 65-nm CMOS ASIC technology and a dynamic range of 21 bits, the conversion time and the circuit area are reduced by about 44% and 30%, respectively, while the conversion time is reduced by 34% for a dynamic range of 37 bits with the circuit area increasing only by 25%. Moreover, the proposed reverse converters outperform the related state of the art for any value of n by up to 70%, according to the figure-of-merit energy per conversion.</abstract><pub>IEEE</pub><doi>10.1109/TVLSI.2012.2219564</doi><tpages>5</tpages></addata></record> |
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subjects | Adders Application specific integrated circuits Application-specific integrated circuit (ASIC) Delay digital hardware design Dynamic range Field programmable gate arrays field-programmable gate array (FPGA) Hardware residue number system (RNS) reverse conversion Very large scale integration |
title | On the Design of RNS Reverse Converters for the Four-Moduli Set +1, 2^-1, 2^, 2^+1}+1 |
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