Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes
This brief presents a NAND Flash memory wear-leveling algorithm that explicitly uses memory raw bit error rate (BER) as the optimization target. Although NAND Flash memory wear-leveling has been well studied, all the existing algorithms aim to equalize the number of programming/erase cycles among al...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2013-07, Vol.21 (7), p.1350-1354 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Pan, Yangyang Dong, Guiqiang Zhang, Tong |
| description | This brief presents a NAND Flash memory wear-leveling algorithm that explicitly uses memory raw bit error rate (BER) as the optimization target. Although NAND Flash memory wear-leveling has been well studied, all the existing algorithms aim to equalize the number of programming/erase cycles among all the memory blocks. Unfortunately, such a conventional design practice becomes increasingly suboptimal as inter-block variation becomes increasingly significant with the technology scaling. This brief presents a dynamic BER-based greedy wear-leveling algorithm that uses BER statistics as the measurement of memory block wear-out pace, and guides dynamic memory block data swapping to fully maximize the wear-leveling efficiency. Simulations have been carried out to quantitatively demonstrate its advantages over existing wear-leveling algorithms. |
| doi_str_mv | 10.1109/TVLSI.2012.2210256 |
| format | Article |
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Although NAND Flash memory wear-leveling has been well studied, all the existing algorithms aim to equalize the number of programming/erase cycles among all the memory blocks. Unfortunately, such a conventional design practice becomes increasingly suboptimal as inter-block variation becomes increasingly significant with the technology scaling. This brief presents a dynamic BER-based greedy wear-leveling algorithm that uses BER statistics as the measurement of memory block wear-out pace, and guides dynamic memory block data swapping to fully maximize the wear-leveling efficiency. Simulations have been carried out to quantitatively demonstrate its advantages over existing wear-leveling algorithms.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2012.2210256</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Algorithm design and analysis ; Applied sciences ; Bit error rate ; Circuit properties ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Error rate ; Exact sciences and technology ; Flash memory ; Heuristic algorithms ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; process variation ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Although NAND Flash memory wear-leveling has been well studied, all the existing algorithms aim to equalize the number of programming/erase cycles among all the memory blocks. Unfortunately, such a conventional design practice becomes increasingly suboptimal as inter-block variation becomes increasingly significant with the technology scaling. This brief presents a dynamic BER-based greedy wear-leveling algorithm that uses BER statistics as the measurement of memory block wear-out pace, and guides dynamic memory block data swapping to fully maximize the wear-leveling efficiency. Simulations have been carried out to quantitatively demonstrate its advantages over existing wear-leveling algorithms.</description><subject>Algorithm design and analysis</subject><subject>Applied sciences</subject><subject>Bit error rate</subject><subject>Circuit properties</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Error rate</subject><subject>Exact sciences and technology</subject><subject>Flash memory</subject><subject>Heuristic algorithms</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>process variation</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>solid state drive</subject><subject>Strontium</subject><subject>Very large scale integration</subject><subject>wear leveling</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1Lw0AQhhdRsFb_gF724jF1v_J11NLaQlSwtR7DZHe2jaRJ2S1C_r1bWzqXGXjmGYaXkHvORpyz_Gm5KhbzkWBcjITgTMTJBRnwOE6jPNRlmFkioyyga3Lj_Q9jXKmcDchq4lzn6CfsMXoBj4Z-I7iowF9s6nZNbYAttIZOG_Ab-obbzvUU9nRWrzdNTxcamiAtUW_arunWPX3vDPpbcmWh8Xh36kPyNZ0sx7Oo-Hidj5-LSEuV7KOMMZ0bwWSaJ1ZxtAaETjMLcSWMyKRJjKokGKkgzassTrWsJNOY2ApQZ0wOiTje1a7z3qEtd67egutLzspDMuV_MuUhmfKUTJAej9IOfHjfOmh17c-mSGPJM8nD3sNxr0bEM05EzlSgf-5IbNo</recordid><startdate>20130701</startdate><enddate>20130701</enddate><creator>Pan, Yangyang</creator><creator>Dong, Guiqiang</creator><creator>Zhang, Tong</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20130701</creationdate><title>Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes</title><author>Pan, Yangyang ; Dong, Guiqiang ; Zhang, Tong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c346t-800c9d203796f41efda2c78fa5b2d283d6d4b3ad34a79b857c3b30ce6fbaec803</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Algorithm design and analysis</topic><topic>Applied sciences</topic><topic>Bit error rate</topic><topic>Circuit properties</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Error rate</topic><topic>Exact sciences and technology</topic><topic>Flash memory</topic><topic>Heuristic algorithms</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>process variation</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>solid state drive</topic><topic>Strontium</topic><topic>Very large scale integration</topic><topic>wear leveling</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Pan, Yangyang</creatorcontrib><creatorcontrib>Dong, Guiqiang</creatorcontrib><creatorcontrib>Zhang, Tong</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pan, Yangyang</au><au>Dong, Guiqiang</au><au>Zhang, Tong</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2013-07-01</date><risdate>2013</risdate><volume>21</volume><issue>7</issue><spage>1350</spage><epage>1354</epage><pages>1350-1354</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>This brief presents a NAND Flash memory wear-leveling algorithm that explicitly uses memory raw bit error rate (BER) as the optimization target. Although NAND Flash memory wear-leveling has been well studied, all the existing algorithms aim to equalize the number of programming/erase cycles among all the memory blocks. Unfortunately, such a conventional design practice becomes increasingly suboptimal as inter-block variation becomes increasingly significant with the technology scaling. This brief presents a dynamic BER-based greedy wear-leveling algorithm that uses BER statistics as the measurement of memory block wear-out pace, and guides dynamic memory block data swapping to fully maximize the wear-leveling efficiency. Simulations have been carried out to quantitatively demonstrate its advantages over existing wear-leveling algorithms.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2012.2210256</doi><tpages>5</tpages></addata></record> |
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| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1350-1354 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithm design and analysis Applied sciences Bit error rate Circuit properties Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Error rate Exact sciences and technology Flash memory Heuristic algorithms Integrated circuits Integrated circuits by function (including memories and processors) process variation Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices solid state drive Strontium Very large scale integration wear leveling |
| title | Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes |
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