Delay-Based Dual-Rail Precharge Logic
This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed lo...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2011-07, Vol.19 (7), p.1147-1153 |
|---|---|
| Hauptverfasser: | , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1153 |
|---|---|
| container_issue | 7 |
| container_start_page | 1147 |
| container_title | IEEE transactions on very large scale integration (VLSI) systems |
| container_volume | 19 |
| creator | Bucci, M. Giancane, L. Luzzi, R. Scotti, G. Trifiletti, A. |
| description | This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rather than in the spatial domain as in a standard dual-rail logic. In this work, a logic family which exploits the proposed concept has been implemented. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and routing capacitances. An improvement in the energy consumption balancing up to 50 times and an area reduction up to 60% with respect to the state of the art have been obtained. |
| doi_str_mv | 10.1109/TVLSI.2010.2046505 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TVLSI_2010_2046505</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5453004</ieee_id><sourcerecordid>2558442451</sourcerecordid><originalsourceid>FETCH-LOGICAL-c460t-b75933bee45bd20b52fdfee0c2642800b7528945e1b61060c9b66cb40e0e11c53</originalsourceid><addsrcrecordid>eNpdkE1PwkAQhjdGExH9A3ohJiRcFmc_2x4V_CBpolH0utkuUywpFHfpgX_vIoSDc5mZzPO-mbyEXDMYMgbZ3fQr_5gMOcSdg9QK1AnpMKUSmsU6jTNoQVPO4JxchLAAYFJm0CH9MdZ2Sx9swFlv3Nqavtuq7r15dN_Wz7GXN_PKXZKz0tYBrw69Sz6fHqejF5q_Pk9G9zl1UsOGFonKhCgQpSpmHArFy1mJCI5ryVOAeOdpJhWyQseHwGWF1q6QgICMOSW6ZLD3Xfvmp8WwMcsqOKxru8KmDYbphCkAUElEb_-hi6b1q_idyZgSOkk5RIjvIeebEDyWZu2rpfVbw8DsgjN_wZldcOYQXBT1D842OFuX3q5cFY5KLgVPOWeRu9lzFSIez0oqASDFL3iacwU</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>915367820</pqid></control><display><type>article</type><title>Delay-Based Dual-Rail Precharge Logic</title><source>IEEE Electronic Library (IEL)</source><creator>Bucci, M. ; Giancane, L. ; Luzzi, R. ; Scotti, G. ; Trifiletti, A.</creator><creatorcontrib>Bucci, M. ; Giancane, L. ; Luzzi, R. ; Scotti, G. ; Trifiletti, A.</creatorcontrib><description>This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rather than in the spatial domain as in a standard dual-rail logic. In this work, a logic family which exploits the proposed concept has been implemented. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and routing capacitances. An improvement in the energy consumption balancing up to 50 times and an area reduction up to 60% with respect to the state of the art have been obtained.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2010.2046505</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Automatic logic units ; Circuit properties ; Cryptography ; Custom design ; Delay ; Design engineering ; Differential amplifiers ; differential power analysis (DPA) ; Digital circuits ; dual-rail logic ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Energy consumption ; Exact sciences and technology ; Logic ; Logic design ; Logic devices ; Power amplifiers ; Power consumption ; Routing ; security ; sense amplifier-based logic (SABL) ; Simulation ; State of the art ; Studies ; three-phase dual-rail precharge logic (TDPL) ; Very large scale integration ; wave dynamic differential logic (WDDL) ; Wire ; Wires</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2011-07, Vol.19 (7), p.1147-1153</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jul 2011</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c460t-b75933bee45bd20b52fdfee0c2642800b7528945e1b61060c9b66cb40e0e11c53</citedby><cites>FETCH-LOGICAL-c460t-b75933bee45bd20b52fdfee0c2642800b7528945e1b61060c9b66cb40e0e11c53</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5453004$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5453004$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=24328221$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Bucci, M.</creatorcontrib><creatorcontrib>Giancane, L.</creatorcontrib><creatorcontrib>Luzzi, R.</creatorcontrib><creatorcontrib>Scotti, G.</creatorcontrib><creatorcontrib>Trifiletti, A.</creatorcontrib><title>Delay-Based Dual-Rail Precharge Logic</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rather than in the spatial domain as in a standard dual-rail logic. In this work, a logic family which exploits the proposed concept has been implemented. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and routing capacitances. An improvement in the energy consumption balancing up to 50 times and an area reduction up to 60% with respect to the state of the art have been obtained.</description><subject>Applied sciences</subject><subject>Automatic logic units</subject><subject>Circuit properties</subject><subject>Cryptography</subject><subject>Custom design</subject><subject>Delay</subject><subject>Design engineering</subject><subject>Differential amplifiers</subject><subject>differential power analysis (DPA)</subject><subject>Digital circuits</subject><subject>dual-rail logic</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Energy consumption</subject><subject>Exact sciences and technology</subject><subject>Logic</subject><subject>Logic design</subject><subject>Logic devices</subject><subject>Power amplifiers</subject><subject>Power consumption</subject><subject>Routing</subject><subject>security</subject><subject>sense amplifier-based logic (SABL)</subject><subject>Simulation</subject><subject>State of the art</subject><subject>Studies</subject><subject>three-phase dual-rail precharge logic (TDPL)</subject><subject>Very large scale integration</subject><subject>wave dynamic differential logic (WDDL)</subject><subject>Wire</subject><subject>Wires</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkE1PwkAQhjdGExH9A3ohJiRcFmc_2x4V_CBpolH0utkuUywpFHfpgX_vIoSDc5mZzPO-mbyEXDMYMgbZ3fQr_5gMOcSdg9QK1AnpMKUSmsU6jTNoQVPO4JxchLAAYFJm0CH9MdZ2Sx9swFlv3Nqavtuq7r15dN_Wz7GXN_PKXZKz0tYBrw69Sz6fHqejF5q_Pk9G9zl1UsOGFonKhCgQpSpmHArFy1mJCI5ryVOAeOdpJhWyQseHwGWF1q6QgICMOSW6ZLD3Xfvmp8WwMcsqOKxru8KmDYbphCkAUElEb_-hi6b1q_idyZgSOkk5RIjvIeebEDyWZu2rpfVbw8DsgjN_wZldcOYQXBT1D842OFuX3q5cFY5KLgVPOWeRu9lzFSIez0oqASDFL3iacwU</recordid><startdate>20110701</startdate><enddate>20110701</enddate><creator>Bucci, M.</creator><creator>Giancane, L.</creator><creator>Luzzi, R.</creator><creator>Scotti, G.</creator><creator>Trifiletti, A.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20110701</creationdate><title>Delay-Based Dual-Rail Precharge Logic</title><author>Bucci, M. ; Giancane, L. ; Luzzi, R. ; Scotti, G. ; Trifiletti, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c460t-b75933bee45bd20b52fdfee0c2642800b7528945e1b61060c9b66cb40e0e11c53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Applied sciences</topic><topic>Automatic logic units</topic><topic>Circuit properties</topic><topic>Cryptography</topic><topic>Custom design</topic><topic>Delay</topic><topic>Design engineering</topic><topic>Differential amplifiers</topic><topic>differential power analysis (DPA)</topic><topic>Digital circuits</topic><topic>dual-rail logic</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Energy consumption</topic><topic>Exact sciences and technology</topic><topic>Logic</topic><topic>Logic design</topic><topic>Logic devices</topic><topic>Power amplifiers</topic><topic>Power consumption</topic><topic>Routing</topic><topic>security</topic><topic>sense amplifier-based logic (SABL)</topic><topic>Simulation</topic><topic>State of the art</topic><topic>Studies</topic><topic>three-phase dual-rail precharge logic (TDPL)</topic><topic>Very large scale integration</topic><topic>wave dynamic differential logic (WDDL)</topic><topic>Wire</topic><topic>Wires</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bucci, M.</creatorcontrib><creatorcontrib>Giancane, L.</creatorcontrib><creatorcontrib>Luzzi, R.</creatorcontrib><creatorcontrib>Scotti, G.</creatorcontrib><creatorcontrib>Trifiletti, A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bucci, M.</au><au>Giancane, L.</au><au>Luzzi, R.</au><au>Scotti, G.</au><au>Trifiletti, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Delay-Based Dual-Rail Precharge Logic</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2011-07-01</date><risdate>2011</risdate><volume>19</volume><issue>7</issue><spage>1147</spage><epage>1153</epage><pages>1147-1153</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rather than in the spatial domain as in a standard dual-rail logic. In this work, a logic family which exploits the proposed concept has been implemented. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and routing capacitances. An improvement in the energy consumption balancing up to 50 times and an area reduction up to 60% with respect to the state of the art have been obtained.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2010.2046505</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2011-07, Vol.19 (7), p.1147-1153 |
| issn | 1063-8210 1557-9999 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_TVLSI_2010_2046505 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Automatic logic units Circuit properties Cryptography Custom design Delay Design engineering Differential amplifiers differential power analysis (DPA) Digital circuits dual-rail logic Electric, optical and optoelectronic circuits Electronic circuits Electronics Energy consumption Exact sciences and technology Logic Logic design Logic devices Power amplifiers Power consumption Routing security sense amplifier-based logic (SABL) Simulation State of the art Studies three-phase dual-rail precharge logic (TDPL) Very large scale integration wave dynamic differential logic (WDDL) Wire Wires |
| title | Delay-Based Dual-Rail Precharge Logic |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T03%3A32%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Delay-Based%20Dual-Rail%20Precharge%20Logic&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Bucci,%20M.&rft.date=2011-07-01&rft.volume=19&rft.issue=7&rft.spage=1147&rft.epage=1153&rft.pages=1147-1153&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2010.2046505&rft_dat=%3Cproquest_RIE%3E2558442451%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=915367820&rft_id=info:pmid/&rft_ieee_id=5453004&rfr_iscdi=true |