A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2010-12, Vol.18 (12), p.1745-1752
Hauptverfasser:	Hoya, Katsuhiko, Takashima, D, Shiratake, S, Ogiwara, R, Miyakawa, T, Shiga, H, Doumae, S M, Ohtsuki, S, Kumura, Y, Shuto, S, Ozaki, T, Yamakawa, K, Kunishima, I, Nitayama, A, Fujii, S
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Bandwidth Burst mode CMOS technology Design. Technologies. Operation analysis. Testing Electronics Energy consumption Error correction Error correction codes Exact sciences and technology Ferroelectric films ferroelectric memory Integrated circuits Integrated circuits by function (including memories and processors) Nonvolatile memory Power amplifiers Random access memory Semiconductor device noise Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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