A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations....
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2008-01, Vol.16 (1), p.14-23 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Myjak, M.J. Delgado-Frias, J.G. |
| description | Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware. |
| doi_str_mv | 10.1109/TVLSI.2007.912080 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TVLSI_2007_912080</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4407540</ieee_id><sourcerecordid>880652053</sourcerecordid><originalsourceid>FETCH-LOGICAL-c421t-597f0b206be3e9591a1fed5c00583ca312436b740f06dbd75e2ac787582a58043</originalsourceid><addsrcrecordid>eNp9kTlPxDAQhSMEEucPQDQWBTRkGV-JQ7fcSItAXK3lOJPFsOss9qbg3-NlEQUF08wU35vRvJdluxQGlEJ1_PQyerwZMIByUFEGClayDSplmVepVtMMBc8Vo7Cebcb4BkCFqGAjs0Nyi43rp_lVMM6TB7Sdb924D6aeIBkG--rmaOd9QNJ2gZw_3p-QxS1yjtGN_RE5RW9fpya8k1szmzk_PiLGN-QeQ-KnxlvcztZaM4m489O3sufLi6ez63x0d3VzNhzlVjA6z2VVtlAzKGrkWMmKGtpiIy2AVNwaTpngRV0KaKFo6qaUyIwtVSkVM1KB4FvZ4XLvLHQfPca5nrpocTIxHrs-aqWgkAwkT-TBvyQXBaVFUSVw_w_41vXBpy90spmDYmIB0SVkQxdjwFbPgkuOfGoKepGO_k5HL9LRy3SSZm-pcYj4ywsBpRTAvwBZI4j7</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912308249</pqid></control><display><type>article</type><title>A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance</title><source>IEEE Electronic Library (IEL)</source><creator>Myjak, M.J. ; Delgado-Frias, J.G.</creator><creatorcontrib>Myjak, M.J. ; Delgado-Frias, J.G.</creatorcontrib><description>Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2007.912080</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Adders ; Architecture ; Computer programs ; Digital signal processing ; Digital signal processing (DSP) ; Field programmable gate arrays ; floating-point arithmetic ; Hardware ; Integrated circuits ; Mathematical analysis ; Mathematical models ; Mathematics ; medium-grain reconfigurable hardware ; Modules ; Multiprocessor interconnection networks ; Reconfigurable architectures ; Software tools ; synthesis tools ; Table lookup ; Very large scale integration</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2008-01, Vol.16 (1), p.14-23</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2008</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c421t-597f0b206be3e9591a1fed5c00583ca312436b740f06dbd75e2ac787582a58043</citedby><cites>FETCH-LOGICAL-c421t-597f0b206be3e9591a1fed5c00583ca312436b740f06dbd75e2ac787582a58043</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4407540$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4407540$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Myjak, M.J.</creatorcontrib><creatorcontrib>Delgado-Frias, J.G.</creatorcontrib><title>A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.</description><subject>Adders</subject><subject>Architecture</subject><subject>Computer programs</subject><subject>Digital signal processing</subject><subject>Digital signal processing (DSP)</subject><subject>Field programmable gate arrays</subject><subject>floating-point arithmetic</subject><subject>Hardware</subject><subject>Integrated circuits</subject><subject>Mathematical analysis</subject><subject>Mathematical models</subject><subject>Mathematics</subject><subject>medium-grain reconfigurable hardware</subject><subject>Modules</subject><subject>Multiprocessor interconnection networks</subject><subject>Reconfigurable architectures</subject><subject>Software tools</subject><subject>synthesis tools</subject><subject>Table lookup</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kTlPxDAQhSMEEucPQDQWBTRkGV-JQ7fcSItAXK3lOJPFsOss9qbg3-NlEQUF08wU35vRvJdluxQGlEJ1_PQyerwZMIByUFEGClayDSplmVepVtMMBc8Vo7Cebcb4BkCFqGAjs0Nyi43rp_lVMM6TB7Sdb924D6aeIBkG--rmaOd9QNJ2gZw_3p-QxS1yjtGN_RE5RW9fpya8k1szmzk_PiLGN-QeQ-KnxlvcztZaM4m489O3sufLi6ez63x0d3VzNhzlVjA6z2VVtlAzKGrkWMmKGtpiIy2AVNwaTpngRV0KaKFo6qaUyIwtVSkVM1KB4FvZ4XLvLHQfPca5nrpocTIxHrs-aqWgkAwkT-TBvyQXBaVFUSVw_w_41vXBpy90spmDYmIB0SVkQxdjwFbPgkuOfGoKepGO_k5HL9LRy3SSZm-pcYj4ywsBpRTAvwBZI4j7</recordid><startdate>200801</startdate><enddate>200801</enddate><creator>Myjak, M.J.</creator><creator>Delgado-Frias, J.G.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>200801</creationdate><title>A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance</title><author>Myjak, M.J. ; Delgado-Frias, J.G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c421t-597f0b206be3e9591a1fed5c00583ca312436b740f06dbd75e2ac787582a58043</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Adders</topic><topic>Architecture</topic><topic>Computer programs</topic><topic>Digital signal processing</topic><topic>Digital signal processing (DSP)</topic><topic>Field programmable gate arrays</topic><topic>floating-point arithmetic</topic><topic>Hardware</topic><topic>Integrated circuits</topic><topic>Mathematical analysis</topic><topic>Mathematical models</topic><topic>Mathematics</topic><topic>medium-grain reconfigurable hardware</topic><topic>Modules</topic><topic>Multiprocessor interconnection networks</topic><topic>Reconfigurable architectures</topic><topic>Software tools</topic><topic>synthesis tools</topic><topic>Table lookup</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Myjak, M.J.</creatorcontrib><creatorcontrib>Delgado-Frias, J.G.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Myjak, M.J.</au><au>Delgado-Frias, J.G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2008-01</date><risdate>2008</risdate><volume>16</volume><issue>1</issue><spage>14</spage><epage>23</epage><pages>14-23</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2007.912080</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2008-01, Vol.16 (1), p.14-23 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Adders Architecture Computer programs Digital signal processing Digital signal processing (DSP) Field programmable gate arrays floating-point arithmetic Hardware Integrated circuits Mathematical analysis Mathematical models Mathematics medium-grain reconfigurable hardware Modules Multiprocessor interconnection networks Reconfigurable architectures Software tools synthesis tools Table lookup Very large scale integration |
| title | A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T20%3A40%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Medium-Grain%20Reconfigurable%20Architecture%20for%20DSP:%20VLSI%20Design,%20Benchmark%20Mapping,%20and%20Performance&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Myjak,%20M.J.&rft.date=2008-01&rft.volume=16&rft.issue=1&rft.spage=14&rft.epage=23&rft.pages=14-23&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2007.912080&rft_dat=%3Cproquest_RIE%3E880652053%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=912308249&rft_id=info:pmid/&rft_ieee_id=4407540&rfr_iscdi=true |