Device-Aware Yield-Centric Dual- V Design Under Parameter Variations in Nanoscale Technologies

Dual-V t design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different leakage components (subthreshold, gate and junction...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2007-06, Vol.15 (6), p.660-671
Hauptverfasser:	Agarwal, A., Kunhyuk Kang, Bhunia, S., Gallagher, J.D., Roy, K.
Format:	Artikel
Sprache:	eng
Schlagworte:	Band-to-band tunneling (BTBT) leakage Circuits CMOS technology Delay Design engineering Design methodology Doping dual- V_{t} design Power dissipation Power engineering and energy process variation Subthreshold current Tunneling
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