Device-Aware Yield-Centric Dual- V Design Under Parameter Variations in Nanoscale Technologies

Dual-V t design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different leakage components (subthreshold, gate and junction tunneling) to become significant portion of total power dissipation in CMOS circuits. High-V t devices are expected to have high junction tunneling current (due to stronger halo doping) compared to low-V t devices, which in the worst case can increase the total leakage in dual-V t design. Moreover, process parameter variations (and in turn V t variations) are expected to be significantly high in sub-50-nm technology regime, which can severely affect the yield. In this paper, we propose a device aware simultaneous sizing and dual-V t design methodology that considers each component of leakage and the impact of process variation (on both delay and leakage power) to minimize the total leakage while ensuring a target yield. Our results show that conventional dual-V t design can overestimate leakage savings by 36% while incurring 17% average yield loss in 50-nm predictive technology. The proposed scheme results in 10%-20% extra leakage power savings compared to conventional dual-V t design, while ensuring target yield. This paper also shows that nonscalability of the present way of realizing high-V t devices results in negligible power savings beyond 25-nm technology. Hence, different dual-V t process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-V t designs in future technologies.