Fast comparisons of circuit implementations
Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor s...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2005-12, Vol.13 (12), p.1329-1339 |
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| container_end_page | 1339 |
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| container_issue | 12 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Karandikar, S.K. Sapatnekar, S.S. |
| description | Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations-the minimum achievable delay and the cost of achieving a target delay-and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the tradeoffs between multiple functionally identical implementations, and size only the selected implementation. |
| doi_str_mv | 10.1109/TVLSI.2005.862727 |
| format | Article |
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Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations-the minimum achievable delay and the cost of achieving a target delay-and show how these can be estimated without running a sizing tool. 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Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations-the minimum achievable delay and the cost of achieving a target delay-and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the tradeoffs between multiple functionally identical implementations, and size only the selected implementation.</description><subject>Applied sciences</subject><subject>Circuit optimization</subject><subject>Circuit synthesis</subject><subject>cost-delay tradeoffs</subject><subject>Costs</subject><subject>Delay estimation</subject><subject>Design optimization</subject><subject>Dynamic programming</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>gate sizing</subject><subject>Logic gates</subject><subject>Logic programming</subject><subject>logical effort</subject><subject>performance estimation</subject><subject>Routing</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Timing</topic><topic>transistor sizing</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Karandikar, S.K.</creatorcontrib><creatorcontrib>Sapatnekar, S.S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Karandikar, S.K.</au><au>Sapatnekar, S.S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Fast comparisons of circuit implementations</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2005-12-01</date><risdate>2005</risdate><volume>13</volume><issue>12</issue><spage>1329</spage><epage>1339</epage><pages>1329-1339</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. 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| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2005-12, Vol.13 (12), p.1329-1339 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit optimization Circuit synthesis cost-delay tradeoffs Costs Delay estimation Design optimization Dynamic programming Electronics Exact sciences and technology gate sizing Logic gates Logic programming logical effort performance estimation Routing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Timing transistor sizing Transistors |
| title | Fast comparisons of circuit implementations |
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