A case for asymmetric-cell cache memories

In this paper, we make the case for building high-performance asymmetric-cell caches (ACCs) that employ recently-proposed asymmetric SRAMs to reduce leakage proportionally to the number of resident zero bits. Because ACCs target memory value content (independent of cell activity and access patterns)...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2005-07, Vol.13 (7), p.877-881
Hauptverfasser:	Moshovos, A., Falsafi, B., Najm, F.N., Azizi, N.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Cache memories Circuits Clocks Computer aided software engineering Computer architecture Computers, microcomputers Cyclic redundancy check Delay Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Hardware high performance Integrated circuits Integrated circuits by function (including memories and processors) leakage power reduction Magnetic and optical mass memories Optical devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Storage and reproduction of information Telecommunication computing Very large scale integration
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