A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation ci...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2005-06, Vol.13 (6), p.686-695
Hauptverfasser:	Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang
Format:	Artikel
Sprache:	eng
Schlagworte:	Adders Arithmetic Circuit simulation CMOS digital integrated circuits CMOS logic circuits Delay digital arithmetic Hybrid power systems Logic circuits Logic design logic devices Switching circuits Voltage
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