Execution cache-based microarchitecture for power-efficient superscalar processors
This paper investigates a possible solution to the problem of power consumption in superscalar, out-of-order processors by proposing a new microarchitecture, specifically designed to reduce increasing power requirements of high-end processors. More precisely, we show that by modifying the well-estab...
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Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2005-01, Vol.13 (1), p.14-26 |
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Sprache: | eng |
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