Array Test Structures for Gate Dielectric Integrity Measurements and Statistics

An array test structure for highly parallelized stressing and measurements of ultrathin MOS gate dielectrics is presented. The array test structure consisting of thousands of NMOS devices under test (DUTs) provides a large and significant statistical base for analysis of dielectric breakdown and the...

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Veröffentlicht in:	IEEE transactions on semiconductor manufacturing 2012-05, Vol.25 (2), p.130-135
Hauptverfasser:	Hafkemeyer, K. M., Domdey, A., Schroeder, D., Krautschneider, W. H.
Format:	Artikel
Sprache:	eng
Schlagworte:	Arrays Current measurement Degradation dielectric breakdown Dielectrics Gates Logic Logic gates Metal oxide semiconductors MOS devices semiconductor device reliability Semiconductors Stress Transistors Tunneling
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