Approach for a Standardized Methodology for Multisite Processing of 300-mm Wafers at R&D Sites
This paper describes the objectives and results of a joint European project named FLYING WAFER. The goal of the project was to provide a methodology for interlinking European R&D centers in micro and nano technologies to a distributed 300-mm CMOS R&D line. The project was carried out as a fe...
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| Veröffentlicht in: | IEEE transactions on semiconductor manufacturing 2007-08, Vol.20 (3), p.215-221 |
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| creator | Oechsner, R. Pfeffer, M. Frickinger, J. Schellenberger, M. Roeder, G. Pfitzner, L. Ryssel, H. Fritzsche, M. Kaushik, V. Renaud, D. Danel, A. Claeys, C. Bearda, T. Lering, M. Graef, M. Murphy, B. Walther, H. Hury, S. |
| description | This paper describes the objectives and results of a joint European project named FLYING WAFER. The goal of the project was to provide a methodology for interlinking European R&D centers in micro and nano technologies to a distributed 300-mm CMOS R&D line. The project was carried out as a feasibility study. Therefore, the results provide a model and concept which has the potential of guaranteeing a safe and fast exchange of wafers and data between European R&D nodes to allow multisite processing. An implementation phase is planned as a second step. |
| doi_str_mv | 10.1109/TSM.2007.901828 |
| format | Article |
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The goal of the project was to provide a methodology for interlinking European R&D centers in micro and nano technologies to a distributed 300-mm CMOS R&D line. The project was carried out as a feasibility study. Therefore, the results provide a model and concept which has the potential of guaranteeing a safe and fast exchange of wafers and data between European R&D nodes to allow multisite processing. An implementation phase is planned as a second step.</description><identifier>ISSN: 0894-6507</identifier><identifier>EISSN: 1558-2345</identifier><identifier>DOI: 10.1109/TSM.2007.901828</identifier><identifier>CODEN: ITSMED</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>300 mm ; Applied sciences ; CMOS ; CMOS technology ; Costs ; Design. Technologies. Operation analysis. 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The goal of the project was to provide a methodology for interlinking European R&D centers in micro and nano technologies to a distributed 300-mm CMOS R&D line. The project was carried out as a feasibility study. Therefore, the results provide a model and concept which has the potential of guaranteeing a safe and fast exchange of wafers and data between European R&D nodes to allow multisite processing. An implementation phase is planned as a second step.</description><subject>300 mm</subject><subject>Applied sciences</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Costs</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Flying</subject><subject>Integrated circuits</subject><subject>Manufacturing industries</subject><subject>Manufacturing processes</subject><subject>Methodology</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Microelectronics</subject><subject>Multisite processing</subject><subject>Nanocomposites</subject><subject>Nanomaterials</subject><subject>Nanostructure</subject><subject>Nanotechnology</subject><subject>Research and development</subject><subject>Semiconductor device manufacture</subject><subject>Semiconductor device modeling</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Flying</topic><topic>Integrated circuits</topic><topic>Manufacturing industries</topic><topic>Manufacturing processes</topic><topic>Methodology</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Microelectronics</topic><topic>Multisite processing</topic><topic>Nanocomposites</topic><topic>Nanomaterials</topic><topic>Nanostructure</topic><topic>Nanotechnology</topic><topic>Research and development</topic><topic>Semiconductor device manufacture</topic><topic>Semiconductor device modeling</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. 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| subjects | 300 mm Applied sciences CMOS CMOS technology Costs Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Flying Integrated circuits Manufacturing industries Manufacturing processes Methodology Microelectronic fabrication (materials and surfaces technology) Microelectronics Multisite processing Nanocomposites Nanomaterials Nanostructure Nanotechnology Research and development Semiconductor device manufacture Semiconductor device modeling Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices semiconductor manufacturing Semiconductors Technological innovation Wafers |
| title | Approach for a Standardized Methodology for Multisite Processing of 300-mm Wafers at R&D Sites |
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