A Clamped Interlocking Isolated Resonant Gate Driver for High-Frequency LLC-DCX
The paper proposes a clamped interlocking isolated resonant gate driver (CIRGD) to provide multiple isolated complementary drive signals for the LLC DC transformer (LLCDCX). The CIRGD clamps the gate voltage to 0∼Vg using clamped MOSFETs, reducing conduction loss caused by the circulation current in...
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| Veröffentlicht in: | IEEE transactions on power electronics 2024-04, Vol.39 (4), p.1-14 |
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| creator | Zhou, Ziyan Luo, Qiang Qian, Qinsong Dong, Tianhao Sun, Yuefei Wang, Yufan Sun, Weifeng |
| description | The paper proposes a clamped interlocking isolated resonant gate driver (CIRGD) to provide multiple isolated complementary drive signals for the LLC DC transformer (LLCDCX). The CIRGD clamps the gate voltage to 0∼Vg using clamped MOSFETs, reducing conduction loss caused by the circulation current in the drive circuit and further improving system efficiency. With appropriate parameter design, the CIRGD generates gate drive signals with the necessary deadtime, enabling soft switching of the LLC-DCX. The working principle, parameter design, loss analysis, and comparative study of the CIRGD are presented in detail. Finally, a prototype with an operating frequency of 1.3 MHz, and a power output of 48V-6V/30A was developed. The experimental results show that compared with the traditional voltage source drive circuit, the proposed CIRGD can significantly enhance the efficiency and reduce the gate drive power loss by nearly 85%. |
| doi_str_mv | 10.1109/TPEL.2023.3332876 |
| format | Article |
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The CIRGD clamps the gate voltage to 0∼Vg using clamped MOSFETs, reducing conduction loss caused by the circulation current in the drive circuit and further improving system efficiency. With appropriate parameter design, the CIRGD generates gate drive signals with the necessary deadtime, enabling soft switching of the LLC-DCX. The working principle, parameter design, loss analysis, and comparative study of the CIRGD are presented in detail. Finally, a prototype with an operating frequency of 1.3 MHz, and a power output of 48V-6V/30A was developed. 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(IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c246t-a4c0c49f2819e634ef63696446395f98f140d6cf843b664d36571874ec9d25b73</cites><orcidid>0009-0006-6685-4860 ; 0000-0002-1573-7342 ; 0000-0002-3289-8877 ; 0009-0009-7751-2622 ; 0009-0002-2089-8420</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10319065$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10319065$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zhou, Ziyan</creatorcontrib><creatorcontrib>Luo, Qiang</creatorcontrib><creatorcontrib>Qian, Qinsong</creatorcontrib><creatorcontrib>Dong, Tianhao</creatorcontrib><creatorcontrib>Sun, Yuefei</creatorcontrib><creatorcontrib>Wang, Yufan</creatorcontrib><creatorcontrib>Sun, Weifeng</creatorcontrib><title>A Clamped Interlocking Isolated Resonant Gate Driver for High-Frequency LLC-DCX</title><title>IEEE transactions on power electronics</title><addtitle>TPEL</addtitle><description>The paper proposes a clamped interlocking isolated resonant gate driver (CIRGD) to provide multiple isolated complementary drive signals for the LLC DC transformer (LLCDCX). The CIRGD clamps the gate voltage to 0∼Vg using clamped MOSFETs, reducing conduction loss caused by the circulation current in the drive circuit and further improving system efficiency. With appropriate parameter design, the CIRGD generates gate drive signals with the necessary deadtime, enabling soft switching of the LLC-DCX. The working principle, parameter design, loss analysis, and comparative study of the CIRGD are presented in detail. Finally, a prototype with an operating frequency of 1.3 MHz, and a power output of 48V-6V/30A was developed. The experimental results show that compared with the traditional voltage source drive circuit, the proposed CIRGD can significantly enhance the efficiency and reduce the gate drive power loss by nearly 85%.</description><subject>Circuit design</subject><subject>Clamping</subject><subject>Clamps</subject><subject>Comparative studies</subject><subject>Conduction losses</subject><subject>DC transformer (DCX)</subject><subject>Density measurement</subject><subject>Design parameters</subject><subject>Electric potential</subject><subject>Electric power loss</subject><subject>Gate drivers</subject><subject>high efficiency</subject><subject>high frequency</subject><subject>high power density</subject><subject>Inductors</subject><subject>LLC</subject><subject>Locking</subject><subject>Logic gates</subject><subject>MOSFET</subject><subject>Power system measurements</subject><subject>resonant gate driver</subject><subject>Transformers</subject><subject>Voltage</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkF9LwzAUxYMoOKcfQPAh4HNnbpKmyePo3B8oTGSCb6FLk9nZtTPphH17M7YHny73cs65hx9Cj0BGAES9rN5eixEllI0YY1Rm4goNQHFICJDsGg2IlGkilWK36C6ELSHAUwIDtBzjvCl3e1vhRdtb33Tmu243eBG6puzj9d2Gri3bHs_iiie-_rUeu87jeb35Sqbe_hxsa464KPJkkn_eoxtXNsE-XOYQfUxfV_k8KZazRT4uEkO56JOSG2K4clSCsoJx6wQTSnAumEqdkg44qYRxkrO1ELxiIs1AZtwaVdF0nbEhej7n7n0XG4Reb7uDb-NLTRXNYhqAiio4q4zvQvDW6b2vd6U_aiD6xE2fuOkTN33hFj1PZ09trf2nZ6CISNkfC29mzw</recordid><startdate>20240401</startdate><enddate>20240401</enddate><creator>Zhou, Ziyan</creator><creator>Luo, Qiang</creator><creator>Qian, Qinsong</creator><creator>Dong, Tianhao</creator><creator>Sun, Yuefei</creator><creator>Wang, Yufan</creator><creator>Sun, Weifeng</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The CIRGD clamps the gate voltage to 0∼Vg using clamped MOSFETs, reducing conduction loss caused by the circulation current in the drive circuit and further improving system efficiency. With appropriate parameter design, the CIRGD generates gate drive signals with the necessary deadtime, enabling soft switching of the LLC-DCX. The working principle, parameter design, loss analysis, and comparative study of the CIRGD are presented in detail. Finally, a prototype with an operating frequency of 1.3 MHz, and a power output of 48V-6V/30A was developed. The experimental results show that compared with the traditional voltage source drive circuit, the proposed CIRGD can significantly enhance the efficiency and reduce the gate drive power loss by nearly 85%.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TPEL.2023.3332876</doi><tpages>14</tpages><orcidid>https://orcid.org/0009-0006-6685-4860</orcidid><orcidid>https://orcid.org/0000-0002-1573-7342</orcidid><orcidid>https://orcid.org/0000-0002-3289-8877</orcidid><orcidid>https://orcid.org/0009-0009-7751-2622</orcidid><orcidid>https://orcid.org/0009-0002-2089-8420</orcidid></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Circuit design Clamping Clamps Comparative studies Conduction losses DC transformer (DCX) Density measurement Design parameters Electric potential Electric power loss Gate drivers high efficiency high frequency high power density Inductors LLC Locking Logic gates MOSFET Power system measurements resonant gate driver Transformers Voltage |
| title | A Clamped Interlocking Isolated Resonant Gate Driver for High-Frequency LLC-DCX |
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