A High-Efficiency Fast-Transient LDO With Low-Impedance Transient-Current Enhanced Buffer

This article proposes a new low-impedance transient-current enhanced (LTE) buffer, which is applied for low-dropout regulator (LDO) with large off-chip capacitor. The LTE buffer is based on current-shunt feedback technique and two ac coupling networks, which can achieve an extremely low output imped...

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Veröffentlicht in:IEEE transactions on power electronics 2022-08, Vol.37 (8), p.8976-8987
Hauptverfasser: Zhao, Xiao, Zhang, Qisheng, Xin, Yaping, Li, Shuoyang, Yu, Lanya
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container_issue 8
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container_title IEEE transactions on power electronics
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creator Zhao, Xiao
Zhang, Qisheng
Xin, Yaping
Li, Shuoyang
Yu, Lanya
description This article proposes a new low-impedance transient-current enhanced (LTE) buffer, which is applied for low-dropout regulator (LDO) with large off-chip capacitor. The LTE buffer is based on current-shunt feedback technique and two ac coupling networks, which can achieve an extremely low output impedance and high charging/discharging current of the gate of power transistor at load transient response, while maintaining low-quiescent current consumption under the full-load range. In addition to containing the LTE buffer, the proposed LTE-LDO employs recycling-folded-cascode amplifier as the error amplifier, which has the advantage of high loop gain, loop bandwidth, and current efficiency. Meanwhile, simple Miller compensation with a nulling resistor is employed for frequency compensation and a complete small-signal analysis under different load current conditions is given in this article. This design has been implemented in semiconductor manufacturing international corporation 0.18 \mum complementary metal-oxide-semiconductor process and the experimental results show that the quiescent current consumption is about 48 \muA, and the maximum current efficiency of the LTE-LDO is 99.976\%. The measured transient response shows that under the condition of 1 \muF load capacitance, when the load current changes to 200 mA/100 ns, the output voltage change is 76 mV.
doi_str_mv 10.1109/TPEL.2022.3154598
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The LTE buffer is based on current-shunt feedback technique and two ac coupling networks, which can achieve an extremely low output impedance and high charging/discharging current of the gate of power transistor at load transient response, while maintaining low-quiescent current consumption under the full-load range. In addition to containing the LTE buffer, the proposed LTE-LDO employs recycling-folded-cascode amplifier as the error amplifier, which has the advantage of high loop gain, loop bandwidth, and current efficiency. Meanwhile, simple Miller compensation with a nulling resistor is employed for frequency compensation and a complete small-signal analysis under different load current conditions is given in this article. This design has been implemented in semiconductor manufacturing international corporation 0.18 <inline-formula><tex-math notation="LaTeX">\mu</tex-math></inline-formula>m complementary metal-oxide-semiconductor process and the experimental results show that the quiescent current consumption is about 48 <inline-formula><tex-math notation="LaTeX">\mu</tex-math></inline-formula>A, and the maximum current efficiency of the LTE-LDO is 99.976<inline-formula><tex-math notation="LaTeX">\%</tex-math></inline-formula>. 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The LTE buffer is based on current-shunt feedback technique and two ac coupling networks, which can achieve an extremely low output impedance and high charging/discharging current of the gate of power transistor at load transient response, while maintaining low-quiescent current consumption under the full-load range. In addition to containing the LTE buffer, the proposed LTE-LDO employs recycling-folded-cascode amplifier as the error amplifier, which has the advantage of high loop gain, loop bandwidth, and current efficiency. Meanwhile, simple Miller compensation with a nulling resistor is employed for frequency compensation and a complete small-signal analysis under different load current conditions is given in this article. This design has been implemented in semiconductor manufacturing international corporation 0.18 <inline-formula><tex-math notation="LaTeX">\mu</tex-math></inline-formula>m complementary metal-oxide-semiconductor process and the experimental results show that the quiescent current consumption is about 48 <inline-formula><tex-math notation="LaTeX">\mu</tex-math></inline-formula>A, and the maximum current efficiency of the LTE-LDO is 99.976<inline-formula><tex-math notation="LaTeX">\%</tex-math></inline-formula>. The measured transient response shows that under the condition of 1 <inline-formula><tex-math notation="LaTeX">\mu</tex-math></inline-formula>F load capacitance, when the load current changes to 200 mA/100 ns, the output voltage change is 76 mV.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TPEL.2022.3154598</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0002-9241-7588</orcidid><orcidid>https://orcid.org/0000-0002-6012-7308</orcidid><orcidid>https://orcid.org/0000-0002-6468-3782</orcidid><orcidid>https://orcid.org/0000-0002-0102-582X</orcidid><orcidid>https://orcid.org/0000-0003-4628-5534</orcidid></addata></record>
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1941-0107
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source IEEE Electronic Library (IEL)
subjects Amplification
Amplifiers
Buffers
Cascode devices
CMOS
Compensation
Comprehensive stability analysis
Current efficiency
Efficiency
high efficiency
Impedance
Logic gates
Long Term Evolution
low-dropout regulator (LDO)
low-impedance transient-current enhanced (LTE) buffer
Power consumption
Power semiconductor devices
Power transistors
recycling-folded-cascode (RFC)
Resistance
Small signal analysis
Transient analysis
Transient current
Transient response
Transistors
Voltage
title A High-Efficiency Fast-Transient LDO With Low-Impedance Transient-Current Enhanced Buffer
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