Service-Oriented Architecture on FPGA-Based MPSoC
The integration of software services-oriented architecture (SOA) and hardware multiprocessor system-on-chip (MPSoC) has been pursued for several years. However, designing and implementing a service-oriented system for diverse applications on a single chip has posed significant challenges due to the...
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Veröffentlicht in: | IEEE transactions on parallel and distributed systems 2017-10, Vol.28 (10), p.2993-3006 |
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creator | Chao Wang Xi Li Chen, Yunji Youhui Zhang Diessel, Oliver Xuehai Zhou |
description | The integration of software services-oriented architecture (SOA) and hardware multiprocessor system-on-chip (MPSoC) has been pursued for several years. However, designing and implementing a service-oriented system for diverse applications on a single chip has posed significant challenges due to the heterogeneous architectures, programming interfaces, and software tool chains. To solve the problem, this paper proposes SoSoC, a service-oriented system-on-chip framework that integrates both embedded processors and software defined hardware accelerators s as computing services on a single chip. Modeling and realizing the SOA design principles, SoSoC provides well-defined programming interfaces for programmers to utilize diverse computing resources efficiently. Furthermore, SoSoC can provide task level parallelization and significant speedup to MPSoC chip design paradigms by providing out-of-order execution scheme with hardware accelerators. To evaluate the performance of SoSoC, we implemented a hardware prototype on Xilinx Virtex5 FPGA board with EEMBC benchmarks. Experimental results demonstrate that the service componentization over original version is less than 3 percent, while the speedup for typical software Benchmarks is up to 372x. To show the portability of SoSoC, we implement the convolutional neural network as a case study on both Xilinx Zynq and Altera DE5 FPGA boards. Results show the SoSoC outperforms state-of-the-art literature with great flexibility. |
doi_str_mv | 10.1109/TPDS.2017.2701828 |
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However, designing and implementing a service-oriented system for diverse applications on a single chip has posed significant challenges due to the heterogeneous architectures, programming interfaces, and software tool chains. To solve the problem, this paper proposes SoSoC, a service-oriented system-on-chip framework that integrates both embedded processors and software defined hardware accelerators s as computing services on a single chip. Modeling and realizing the SOA design principles, SoSoC provides well-defined programming interfaces for programmers to utilize diverse computing resources efficiently. Furthermore, SoSoC can provide task level parallelization and significant speedup to MPSoC chip design paradigms by providing out-of-order execution scheme with hardware accelerators. To evaluate the performance of SoSoC, we implemented a hardware prototype on Xilinx Virtex5 FPGA board with EEMBC benchmarks. Experimental results demonstrate that the service componentization over original version is less than 3 percent, while the speedup for typical software Benchmarks is up to 372x. To show the portability of SoSoC, we implement the convolutional neural network as a case study on both Xilinx Zynq and Altera DE5 FPGA boards. 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(IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-6b390749a3bb6a065f0008d311ceb104066f4ca027057c5ae26ea2b77c6203643</citedby><cites>FETCH-LOGICAL-c293t-6b390749a3bb6a065f0008d311ceb104066f4ca027057c5ae26ea2b77c6203643</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7920399$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7920399$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chao Wang</creatorcontrib><creatorcontrib>Xi Li</creatorcontrib><creatorcontrib>Chen, Yunji</creatorcontrib><creatorcontrib>Youhui Zhang</creatorcontrib><creatorcontrib>Diessel, Oliver</creatorcontrib><creatorcontrib>Xuehai Zhou</creatorcontrib><title>Service-Oriented Architecture on FPGA-Based MPSoC</title><title>IEEE transactions on parallel and distributed systems</title><addtitle>TPDS</addtitle><description>The integration of software services-oriented architecture (SOA) and hardware multiprocessor system-on-chip (MPSoC) has been pursued for several years. However, designing and implementing a service-oriented system for diverse applications on a single chip has posed significant challenges due to the heterogeneous architectures, programming interfaces, and software tool chains. To solve the problem, this paper proposes SoSoC, a service-oriented system-on-chip framework that integrates both embedded processors and software defined hardware accelerators s as computing services on a single chip. Modeling and realizing the SOA design principles, SoSoC provides well-defined programming interfaces for programmers to utilize diverse computing resources efficiently. Furthermore, SoSoC can provide task level parallelization and significant speedup to MPSoC chip design paradigms by providing out-of-order execution scheme with hardware accelerators. To evaluate the performance of SoSoC, we implemented a hardware prototype on Xilinx Virtex5 FPGA board with EEMBC benchmarks. Experimental results demonstrate that the service componentization over original version is less than 3 percent, while the speedup for typical software Benchmarks is up to 372x. To show the portability of SoSoC, we implement the convolutional neural network as a case study on both Xilinx Zynq and Altera DE5 FPGA boards. Results show the SoSoC outperforms state-of-the-art literature with great flexibility.</description><subject>Accelerators</subject><subject>Artificial neural networks</subject><subject>Benchmarks</subject><subject>Computation</subject><subject>Computer architecture</subject><subject>Embedded systems</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Multiprocessing</subject><subject>multiprocessor</subject><subject>Parallel processing</subject><subject>Programming</subject><subject>Semiconductor optical amplifiers</subject><subject>Service oriented architecture</subject><subject>Software development tools</subject><subject>State of the art</subject><subject>System on chip</subject><issn>1045-9219</issn><issn>1558-2183</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEFLAzEQhYMoWKs_QLwUPKfOJNlkc6zVVqHSQus5ZNNZ3KLdmmwF_70pLZ5mYN6b9_gYu0UYIoJ9WC2elkMBaIbCAJaiPGM9LIqSCyzled5BFdwKtJfsKqUNAKoCVI_hkuJPE4jPY0PbjtaDUQwfTUeh20catNvBZDEd8Uef8ultsWzH1-yi9p-Jbk6zz94nz6vxC5_Np6_j0YwHYWXHdSUtGGW9rCrtQRc1AJRriRioym1A61oFD7luYULhSWjyojImaAFSK9ln98e_u9h-7yl1btPu4zZHOoFGKW2hhKzCoyrENqVItdvF5svHX4fgDmTcgYw7kHEnMtlzd_Q0RPSvNzbnWiv_AAvFW-M</recordid><startdate>20171001</startdate><enddate>20171001</enddate><creator>Chao Wang</creator><creator>Xi Li</creator><creator>Chen, Yunji</creator><creator>Youhui Zhang</creator><creator>Diessel, Oliver</creator><creator>Xuehai Zhou</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20171001</creationdate><title>Service-Oriented Architecture on FPGA-Based MPSoC</title><author>Chao Wang ; Xi Li ; Chen, Yunji ; Youhui Zhang ; Diessel, Oliver ; Xuehai Zhou</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-6b390749a3bb6a065f0008d311ceb104066f4ca027057c5ae26ea2b77c6203643</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Accelerators</topic><topic>Artificial neural networks</topic><topic>Benchmarks</topic><topic>Computation</topic><topic>Computer architecture</topic><topic>Embedded systems</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Multiprocessing</topic><topic>multiprocessor</topic><topic>Parallel processing</topic><topic>Programming</topic><topic>Semiconductor optical amplifiers</topic><topic>Service oriented architecture</topic><topic>Software development tools</topic><topic>State of the art</topic><topic>System on chip</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chao Wang</creatorcontrib><creatorcontrib>Xi Li</creatorcontrib><creatorcontrib>Chen, Yunji</creatorcontrib><creatorcontrib>Youhui Zhang</creatorcontrib><creatorcontrib>Diessel, Oliver</creatorcontrib><creatorcontrib>Xuehai Zhou</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on parallel and distributed systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chao Wang</au><au>Xi Li</au><au>Chen, Yunji</au><au>Youhui Zhang</au><au>Diessel, Oliver</au><au>Xuehai Zhou</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Service-Oriented Architecture on FPGA-Based MPSoC</atitle><jtitle>IEEE transactions on parallel and distributed systems</jtitle><stitle>TPDS</stitle><date>2017-10-01</date><risdate>2017</risdate><volume>28</volume><issue>10</issue><spage>2993</spage><epage>3006</epage><pages>2993-3006</pages><issn>1045-9219</issn><eissn>1558-2183</eissn><coden>ITDSEO</coden><abstract>The integration of software services-oriented architecture (SOA) and hardware multiprocessor system-on-chip (MPSoC) has been pursued for several years. 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subjects | Accelerators Artificial neural networks Benchmarks Computation Computer architecture Embedded systems Field programmable gate arrays Hardware Multiprocessing multiprocessor Parallel processing Programming Semiconductor optical amplifiers Service oriented architecture Software development tools State of the art System on chip |
title | Service-Oriented Architecture on FPGA-Based MPSoC |
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