A 65 nm Temporally Hardened Flip-Flop Circuit
A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one \tau (the maximum width of a single-event tran...
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| Veröffentlicht in: | IEEE transactions on nuclear science 2016-12, Vol.63 (6), p.2934-2940 |
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| container_title | IEEE transactions on nuclear science |
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| creator | Li, Y.-Q Wang, H.-B Rui Liu Li Chen Nofal, Issam Chen, Q.-Y He, A.-L Gang Guo Baeg, Sang H. Shi-Jie Wen Wong, Richard Qiong Wu Mo Chen |
| description | A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one \tau (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm 2 /mg. Simulation results from the TFIT further validate the experimental results. |
| doi_str_mv | 10.1109/TNS.2016.2608911 |
| format | Article |
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Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one \tau (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm 2 /mg. Simulation results from the TFIT further validate the experimental results.</description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.2016.2608911</identifier><identifier>CODEN: IETNAE</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Alpha rays ; Circuit faults ; Circuits ; Design ; Flip-flop ; Flip-flops ; Latches ; Radiation hardening (electronics) ; SET ; SEU ; Single Event Effects ; Single event upsets ; Soft errors ; temporal hardening ; Transient analysis ; α Radiation</subject><ispartof>IEEE transactions on nuclear science, 2016-12, Vol.63 (6), p.2934-2940</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c427t-326b0fb61e66b5d567101b79f9ab4df970598916f77d052334168646a9133ea83</citedby><cites>FETCH-LOGICAL-c427t-326b0fb61e66b5d567101b79f9ab4df970598916f77d052334168646a9133ea83</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7565582$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7565582$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Li, Y.-Q</creatorcontrib><creatorcontrib>Wang, H.-B</creatorcontrib><creatorcontrib>Rui Liu</creatorcontrib><creatorcontrib>Li Chen</creatorcontrib><creatorcontrib>Nofal, Issam</creatorcontrib><creatorcontrib>Chen, Q.-Y</creatorcontrib><creatorcontrib>He, A.-L</creatorcontrib><creatorcontrib>Gang Guo</creatorcontrib><creatorcontrib>Baeg, Sang H.</creatorcontrib><creatorcontrib>Shi-Jie Wen</creatorcontrib><creatorcontrib>Wong, Richard</creatorcontrib><creatorcontrib>Qiong Wu</creatorcontrib><creatorcontrib>Mo Chen</creatorcontrib><title>A 65 nm Temporally Hardened Flip-Flop Circuit</title><title>IEEE transactions on nuclear science</title><addtitle>TNS</addtitle><description>A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one \tau (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm 2 /mg. Simulation results from the TFIT further validate the experimental results.</description><subject>Alpha rays</subject><subject>Circuit faults</subject><subject>Circuits</subject><subject>Design</subject><subject>Flip-flop</subject><subject>Flip-flops</subject><subject>Latches</subject><subject>Radiation hardening (electronics)</subject><subject>SET</subject><subject>SEU</subject><subject>Single Event Effects</subject><subject>Single event upsets</subject><subject>Soft errors</subject><subject>temporal hardening</subject><subject>Transient analysis</subject><subject>α Radiation</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kDFrwzAQRkVpoWnavdDF0FnpnWSdpDGEOimEdmg6CzmWwcGJXTkZ8u-r4NDpOHjfd8dj7Blhhgj2bfP5PROANBMExiLesAkqZTgqbW7ZBAANt7m19-xhGHZpzRWoCePzjFR22GebsO-76Nv2nK18rMIhVFnRNj0v2q7PFk3cnprjI7urfTuEp-ucsp_ifbNY8fXX8mMxX_NtLvSRS0El1CVhICpVpUgjYKltbX2ZV7XVoGz6kWqtK1BCyhzJUE7eopTBGzllr2NvH7vfUxiObted4iGddGgUCGEF2UTBSG1jNwwx1K6Pzd7Hs0NwFykuSXEXKe4qJUVexkgTQvjHtaKkSsg_NM1ZcA</recordid><startdate>20161201</startdate><enddate>20161201</enddate><creator>Li, Y.-Q</creator><creator>Wang, H.-B</creator><creator>Rui Liu</creator><creator>Li Chen</creator><creator>Nofal, Issam</creator><creator>Chen, Q.-Y</creator><creator>He, A.-L</creator><creator>Gang Guo</creator><creator>Baeg, Sang H.</creator><creator>Shi-Jie Wen</creator><creator>Wong, Richard</creator><creator>Qiong Wu</creator><creator>Mo Chen</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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science</jtitle><stitle>TNS</stitle><date>2016-12-01</date><risdate>2016</risdate><volume>63</volume><issue>6</issue><spage>2934</spage><epage>2940</epage><pages>2934-2940</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one \tau (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm 2 /mg. Simulation results from the TFIT further validate the experimental results.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TNS.2016.2608911</doi><tpages>7</tpages></addata></record> |
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| subjects | Alpha rays Circuit faults Circuits Design Flip-flop Flip-flops Latches Radiation hardening (electronics) SET SEU Single Event Effects Single event upsets Soft errors temporal hardening Transient analysis α Radiation |
| title | A 65 nm Temporally Hardened Flip-Flop Circuit |
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