A Hardened-by-Design Technique for RF Digital Phase-Locked Loops
A RHBD topology for digital phase-locked loops (DPLLs) has been developed for single-event transient (SET) mitigation. By replacing the vulnerable current-based charge pump with a SET-resistant tri-state voltage-switching charge pump and a low-pass filter, the DPLL single-event susceptibility was co...
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| Veröffentlicht in: | IEEE transactions on nuclear science 2006-12, Vol.53 (6), p.3432-3438 |
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| container_issue | 6 |
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| container_title | IEEE transactions on nuclear science |
| container_volume | 53 |
| creator | Loveless, T.D. Massengill, L.W. Bhuva, B.L. Holman, W.T. Witulski, A.F. Boulghassoul, Y. |
| description | A RHBD topology for digital phase-locked loops (DPLLs) has been developed for single-event transient (SET) mitigation. By replacing the vulnerable current-based charge pump with a SET-resistant tri-state voltage-switching charge pump and a low-pass filter, the DPLL single-event susceptibility was considerably reduced, while simultaneously decreasing the lock-in time of the DPLL. The design results in a decreased area requirement with minimal impacts on phase jitter and power consumption. Furthermore, the design eliminates the charge pump as the most vulnerable module and significantly hardens the DPLL |
| doi_str_mv | 10.1109/TNS.2006.886203 |
| format | Article |
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By replacing the vulnerable current-based charge pump with a SET-resistant tri-state voltage-switching charge pump and a low-pass filter, the DPLL single-event susceptibility was considerably reduced, while simultaneously decreasing the lock-in time of the DPLL. The design results in a decreased area requirement with minimal impacts on phase jitter and power consumption. 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By replacing the vulnerable current-based charge pump with a SET-resistant tri-state voltage-switching charge pump and a low-pass filter, the DPLL single-event susceptibility was considerably reduced, while simultaneously decreasing the lock-in time of the DPLL. The design results in a decreased area requirement with minimal impacts on phase jitter and power consumption. Furthermore, the design eliminates the charge pump as the most vulnerable module and significantly hardens the DPLL</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TNS.2006.886203</doi><tpages>7</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Analog single-event transients Charge pumps circuit hardening by design Circuit simulation Circuit topology Clocks Digital digital phase-locked loops Hardening Jitter Phase frequency detector Phase locked loops Power consumption Radio frequencies Radio frequency RF operation Signal generators Topology Voltage Voltage-controlled oscillators |
| title | A Hardened-by-Design Technique for RF Digital Phase-Locked Loops |
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