Photon-Induced Negative Capacitance in Metal Oxide Semiconductor Structures
Design and fabrication of photon-induced negative capacitance is presented. The capacitor is implemented using Silicon on Insulator Metal Oxide Semiconductor platform, where the gate dielectric is made of a nonferroelectric material. Operating at room temperature, when the device is illuminated, in...
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| Veröffentlicht in: | IEEE transactions on nanotechnology 2016-09, Vol.15 (5), p.715-719 |
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| container_title | IEEE transactions on nanotechnology |
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| creator | Fadavi Roudsari, Anita Khodadad, Iman Singh Saini, Simarjeet Anantram, M. P. |
| description | Design and fabrication of photon-induced negative capacitance is presented. The capacitor is implemented using Silicon on Insulator Metal Oxide Semiconductor platform, where the gate dielectric is made of a nonferroelectric material. Operating at room temperature, when the device is illuminated, in depletion mode the total capacitance grows in magnitude to values larger than the geometrical capacitance. We believe this is caused by the trap states existing at the interface of dielectric and semiconductor layers, and present the supporting modeling results. Using our model, we investigate the role of the trap density and light intensity, as well as the device geometry such as gate-ground position and the thickness of the silicon layer. Our model shows the depletion capacitance can grow to values more than three times larger than the geometrical capacitance. |
| doi_str_mv | 10.1109/TNANO.2016.2519897 |
| format | Article |
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Our model shows the depletion capacitance can grow to values more than three times larger than the geometrical capacitance.</description><subject>Capacitors</subject><subject>Electric potential</subject><subject>Electron traps</subject><subject>Interface trap states</subject><subject>Logic gates</subject><subject>MOS capacitor</subject><subject>MOS capacitors</subject><subject>negative capacitance</subject><subject>photo-generation</subject><subject>Quantum capacitance</subject><issn>1536-125X</issn><issn>1941-0085</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1PAjEURRujiYj-Ad1M4nqwn9N2SYgiEcEETNw1nc5DS2CKnY7Rf-8gxNW7i3vuSw5C1wQPCMH6bjkbzuYDikkxoIJopeUJ6hHNSY6xEqddFqzICRVv5-iiadYYE1kI1UNPLx8hhTqf1FXroMpm8G6T_4JsZHfW-WRrB5mvs2dIdpPNv30F2QK23oU9kELMFil2oY3QXKKzld00cHW8ffT6cL8cPebT-XgyGk5zx5hOOWOUSKqsKiW3UnOmAeiqlJZZaSktNXFVqam2FoMDoTAXzklBuSx5iRVmfXR72N3F8NlCk8w6tLHuXhqiGO4WeUG6Fj20XAxNE2FldtFvbfwxBJu9NPMnzeylmaO0Dro5QB4A_gHJlJS8YL-ynWha</recordid><startdate>201609</startdate><enddate>201609</enddate><creator>Fadavi Roudsari, Anita</creator><creator>Khodadad, Iman</creator><creator>Singh Saini, Simarjeet</creator><creator>Anantram, M. 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P.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Photon-Induced Negative Capacitance in Metal Oxide Semiconductor Structures</atitle><jtitle>IEEE transactions on nanotechnology</jtitle><stitle>TNANO</stitle><date>2016-09</date><risdate>2016</risdate><volume>15</volume><issue>5</issue><spage>715</spage><epage>719</epage><pages>715-719</pages><issn>1536-125X</issn><eissn>1941-0085</eissn><coden>ITNECU</coden><abstract>Design and fabrication of photon-induced negative capacitance is presented. The capacitor is implemented using Silicon on Insulator Metal Oxide Semiconductor platform, where the gate dielectric is made of a nonferroelectric material. Operating at room temperature, when the device is illuminated, in depletion mode the total capacitance grows in magnitude to values larger than the geometrical capacitance. We believe this is caused by the trap states existing at the interface of dielectric and semiconductor layers, and present the supporting modeling results. Using our model, we investigate the role of the trap density and light intensity, as well as the device geometry such as gate-ground position and the thickness of the silicon layer. Our model shows the depletion capacitance can grow to values more than three times larger than the geometrical capacitance.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TNANO.2016.2519897</doi><tpages>5</tpages><oa>free_for_read</oa></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Capacitors Electric potential Electron traps Interface trap states Logic gates MOS capacitor MOS capacitors negative capacitance photo-generation Quantum capacitance |
| title | Photon-Induced Negative Capacitance in Metal Oxide Semiconductor Structures |
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