Wafer-applied underfill: flip-chip assembly and reliability
Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to com...
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| Veröffentlicht in: | IEEE transactions on electronics packaging manufacturing 2004-04, Vol.27 (2), p.101-108 |
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| container_title | IEEE transactions on electronics packaging manufacturing |
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| creator | Johnson, R.W. Qing Wang Fei Ding Zhenwei Hou Crane, L. Hao Tang Shi, G. Renzhe Zhao Danvir, J. Jing Qi |
| description | Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125/spl deg/C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented. |
| doi_str_mv | 10.1109/TEPM.2004.839599 |
| format | Article |
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Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125/spl deg/C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented.</description><identifier>ISSN: 1521-334X</identifier><identifier>EISSN: 1558-0822</identifier><identifier>DOI: 10.1109/TEPM.2004.839599</identifier><identifier>CODEN: ITEPFL</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Assembly ; Consumer electronics ; Design. Technologies. Operation analysis. Testing ; Electronic packaging thermal management ; Electronics ; Exact sciences and technology ; Flip-chip ; Integrated circuits ; Manufacturing ; preapplied ; Production facilities ; Sawing ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Space technology ; Surface-mount technology ; Testing ; Testing, measurement, noise and reliability ; Thermal expansion ; underfill ; wafer-applied</subject><ispartof>IEEE transactions on electronics packaging manufacturing, 2004-04, Vol.27 (2), p.101-108</ispartof><rights>2005 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c382t-6aa6ae591dc448fba2f327a4815ae15f86d9f5d67fb14e519ca049365092ee903</citedby><cites>FETCH-LOGICAL-c382t-6aa6ae591dc448fba2f327a4815ae15f86d9f5d67fb14e519ca049365092ee903</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1366493$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1366493$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=16326710$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Johnson, R.W.</creatorcontrib><creatorcontrib>Qing Wang</creatorcontrib><creatorcontrib>Fei Ding</creatorcontrib><creatorcontrib>Zhenwei Hou</creatorcontrib><creatorcontrib>Crane, L.</creatorcontrib><creatorcontrib>Hao Tang</creatorcontrib><creatorcontrib>Shi, G.</creatorcontrib><creatorcontrib>Renzhe Zhao</creatorcontrib><creatorcontrib>Danvir, J.</creatorcontrib><creatorcontrib>Jing Qi</creatorcontrib><title>Wafer-applied underfill: flip-chip assembly and reliability</title><title>IEEE transactions on electronics packaging manufacturing</title><addtitle>TEPM</addtitle><description>Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125/spl deg/C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented.</description><subject>Applied sciences</subject><subject>Assembly</subject><subject>Consumer electronics</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronic packaging thermal management</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Flip-chip</subject><subject>Integrated circuits</subject><subject>Manufacturing</subject><subject>preapplied</subject><subject>Production facilities</subject><subject>Sawing</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Space technology</subject><subject>Surface-mount technology</subject><subject>Testing</subject><subject>Testing, measurement, noise and reliability</subject><subject>Thermal expansion</subject><subject>underfill</subject><subject>wafer-applied</subject><issn>1521-334X</issn><issn>1558-0822</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkM1r20AQxUVpoWnae6EXEWhucnb2S7vJKRgnDSSkB4f0toylWbpmLSu71sH_faQ4YOilpxmY37yZ94riO7AZALMXy8XvhxlnTM6MsMraD8UJKGUqZjj_OPUcKiHkn8_Fl5zXjIFUnJ8UV8_oKVXY9zFQWw5dS8mHGC9LH0NfNX9DX2LOtFnFfYldWyaKAVchht3-a_HJY8z07b2eFk83i-X8V3X_eHs3v76vGmH4rtKIGklZaBspjV8h94LXKA0oJFDe6NZ61erar0CSAtsgk1ZoxSwnskycFucH3T5tXwbKO7cJuaEYsaPtkB23Qghg9f9BU0MNlo_g2T_gejukbjThjBmfBvl2lh2gJm1zTuRdn8IG094Bc1PmbsrcTZm7Q-bjys93XcwNRp-wa0I-7mnBdQ2T9I8DF4joOBZaj8bFK5VNiMQ</recordid><startdate>20040401</startdate><enddate>20040401</enddate><creator>Johnson, R.W.</creator><creator>Qing Wang</creator><creator>Fei Ding</creator><creator>Zhenwei Hou</creator><creator>Crane, L.</creator><creator>Hao Tang</creator><creator>Shi, G.</creator><creator>Renzhe Zhao</creator><creator>Danvir, J.</creator><creator>Jing Qi</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Testing</topic><topic>Electronic packaging thermal management</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Flip-chip</topic><topic>Integrated circuits</topic><topic>Manufacturing</topic><topic>preapplied</topic><topic>Production facilities</topic><topic>Sawing</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Space technology</topic><topic>Surface-mount technology</topic><topic>Testing</topic><topic>Testing, measurement, noise and reliability</topic><topic>Thermal expansion</topic><topic>underfill</topic><topic>wafer-applied</topic><toplevel>online_resources</toplevel><creatorcontrib>Johnson, R.W.</creatorcontrib><creatorcontrib>Qing Wang</creatorcontrib><creatorcontrib>Fei Ding</creatorcontrib><creatorcontrib>Zhenwei Hou</creatorcontrib><creatorcontrib>Crane, L.</creatorcontrib><creatorcontrib>Hao Tang</creatorcontrib><creatorcontrib>Shi, G.</creatorcontrib><creatorcontrib>Renzhe Zhao</creatorcontrib><creatorcontrib>Danvir, J.</creatorcontrib><creatorcontrib>Jing Qi</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><jtitle>IEEE transactions on electronics packaging manufacturing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Johnson, R.W.</au><au>Qing Wang</au><au>Fei Ding</au><au>Zhenwei Hou</au><au>Crane, L.</au><au>Hao Tang</au><au>Shi, G.</au><au>Renzhe Zhao</au><au>Danvir, J.</au><au>Jing Qi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Wafer-applied underfill: flip-chip assembly and reliability</atitle><jtitle>IEEE transactions on electronics packaging manufacturing</jtitle><stitle>TEPM</stitle><date>2004-04-01</date><risdate>2004</risdate><volume>27</volume><issue>2</issue><spage>101</spage><epage>108</epage><pages>101-108</pages><issn>1521-334X</issn><eissn>1558-0822</eissn><coden>ITEPFL</coden><abstract>Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125/spl deg/C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TEPM.2004.839599</doi><tpages>8</tpages></addata></record> |
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| subjects | Applied sciences Assembly Consumer electronics Design. Technologies. Operation analysis. Testing Electronic packaging thermal management Electronics Exact sciences and technology Flip-chip Integrated circuits Manufacturing preapplied Production facilities Sawing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Space technology Surface-mount technology Testing Testing, measurement, noise and reliability Thermal expansion underfill wafer-applied |
| title | Wafer-applied underfill: flip-chip assembly and reliability |
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