Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis

Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part,...

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Veröffentlicht in:	IEEE transactions on electromagnetic compatibility 2010-05, Vol.52 (2), p.381-391
Hauptverfasser:	Hao-Hsiang Chuang, Wei-Da Guo, Yu-Hsiang Lin, Hsin-Shu Chen, Yi-Chang Lu, Yung-Shou Cheng, Ming-Zhang Hong, Chun-Huang Yu, Wen-Chang Cheng, Yen-Ping Chou, Chuan-Jen Chang, Ku, Joseph, Tzong-Lin Wu, Ruey-Beei Wu
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitance Data buses Discontinuity Double-data-rate synchronous dynamic RAM (DDR SDRAM) eye diagram High speed Impedance Integrated circuit modeling Integrity Mathematical models model extraction Modules Packages Polyimide resins power distribution network (PDN) power integrity (PI) signal integrity (SI) Silicon Strategy Topology Transmission line measurements
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