Optimization of Asymmetries in Source/Drain Configurations and Tapered Channels for Vertical-Transport Silicon Nanosheet FETs

This article presents a thorough investigation of the optimization of asymmetries in vertical-transport nanosheet field-effect transistors (VFETs), considering both asymmetric source/drain (S/D) structures and channel tapering. For asymmetric S/D configurations, n-type FETs (nFETs) exhibit smaller R...

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Veröffentlicht in:	IEEE transactions on electron devices 2025-01, Vol.72 (1), p.75-82
Hauptverfasser:	Jeong, Jinsu, Lee, Sanguk, Baek, Rock-Hyun
Format:	Artikel
Sprache:	eng
Schlagworte:	Asymmetric source/drain (S/D) structures asymmetric vertical-transport nanosheet field-effect transistor (VFET) Asymmetry channel tapering Configurations Delay Design optimization device optimization Electric potential Field effect transistors Gallium arsenide gate all around (GAA) Logic gates Mathematical models Nanoscale devices nanosheet (NS) Nanosheets Optimization Resistance Semiconductor devices Semiconductor process modeling Stress System on chip Tapering technology computer-aided design (TCAD) simulation VFET Voltage drop
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