Impact of Process Sequence and Device Architecture on Mechanical Stress and Electrical Properties of 3-D Nand Flash

The impact of the process sequence and device architecture of pure-metal replacement gate (PMRG) nand and terabit cell array transistor (TCAT) on mechanical stress and electrical properties of the devices was analyzed using Sentaurus technology computer-aided design (TCAD) simulation. In the case of PMRG, Al2O3 was deposited before the polysilicon channel. This process sequence resulted in a significant change in channel stress concerning the deposition temperature of tungsten ( {T}_{\text {D,W}}) compared to Al2O3 ( {T}_{\text {D,Al2O3}}) . In contrast, in TCAT, the channel stress relied on {T}_{\text {D,Al2O3}} than {T}_{\text {D,W}} . This highlights that the process sequence strongly affects channel stress. Meanwhile, the material in contact between adjacent W gates differed between PMRG and TCAT (SiO2 in PMRG and Al2O3/Si3N4/SiO2 in TCAT). This difference in device architecture determines the trend of channel stress concerning {T}_{\text {D,W}} . Consequently, the ON-current increased proportionally with the increase in channel tensile stress. Specifically, in PMRG, the ON-current increased as {T}_{\text {D,Al2O3}} increased, and {T}_{\text {D,W}} decreased. Additionally, in TCAT, the ON-current increased as both {T}_{\text {D,Al2O3}} , and {T}_{\text {D,W}} increased. Moreover, when the deposition temperature of each material was set to reach the highest channel tensile stress, PMRG and TCAT showed ON-current enhancements of 7.62% and 8.15%, respectively. In addition, the channel stress trends using molybdenum (Mo) metal were similar to those using W metal.