CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Complementary field-effect transistor (CFET) has successfully boosted the area scaling of static random access memory (SRAM) bitcell due to its stacked architecture. However, this architecture introduces taller via connection from the frontside back-end-of-line (BEOL) signals to the bottom pass-gate...

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Veröffentlicht in:	IEEE transactions on electron devices 2023-10, Vol.70 (10), p.1-8
Hauptverfasser:	Liu, Hsiao-Hsuan, Schuddinck, Pieter, Pei, Zhenlin, Verschueren, Lynn, Mertens, Hans, Salahuddin, Shairfe M., Hiblot, Gaspard, Xiang, Yang, Chan, Boon Teik, Subramanian, Sujith, Weckx, Pieter, Hellings, Geert, Bardon, Marie Garcia, Ryckaert, Julien, Pan, Chenyun, Catthoor, Francky
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitance Complementary field-effect transistor (CFET) Computer architecture Design optimization design technology co-optimization (DTCO) Field effect transistors Logic gates Metals MONOS devices Parasitics (electronics) R&D Random access memory Research & development Routing scaling Semiconductor devices Static random access memory static random access memory (SRAM) Substrates
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