Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions
Combined effects of asymmetric defect distributions and asymmetric gate work functions (WFs) on the performances of self-aligned dual-gate poly-Si TFTs are investigated. Normally, small grains with plentiful grain boundaries (GBs) or other structural defects appear at different positions of the poly...
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| Veröffentlicht in: | IEEE transactions on electron devices 2023-06, Vol.70 (6), p.1-4 |
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| creator | Hsu, Chih-Chieh Li, Jin-Xian Huang, Po-Cheng Jhang, Wun-Ciang Joodaki, Mojtaba |
| description | Combined effects of asymmetric defect distributions and asymmetric gate work functions (WFs) on the performances of self-aligned dual-gate poly-Si TFTs are investigated. Normally, small grains with plentiful grain boundaries (GBs) or other structural defects appear at different positions of the poly-Si film, which is dependent on the growth process of the film. Subgap states of acceptor-like tail, acceptor-like deep-level, donor-like tail, and donor-like deep-level states are used to emulate the defects. Two sets of density of states (DOS) are employed. We find that defects at different positions of the source-side and drain-side channels exhibit different influences on TFT performance and the influences are dependent on the WFs of the gates. TFTs with a higher gate WF can have a higher tolerance to the depth of the defect region. Besides the electrical characteristics, the combined effects of defects and gate WFs on current density distributions and electric field distributions in the channel regions are explored. The performance variations caused by the asymmetric defects along with asymmetric gate WFs can be explained. |
| doi_str_mv | 10.1109/TED.2023.3269004 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TED_2023_3269004</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10114631</ieee_id><sourcerecordid>2819499260</sourcerecordid><originalsourceid>FETCH-LOGICAL-c245t-abf509a0d14cafc84d8227b9e99978612fdc78b1dde471bb6e53ee75a8871f363</originalsourceid><addsrcrecordid>eNpNkDtPwzAURi0EEqWwMzBYYk7xK449Vn2BVImBoI6W49iqS5oU2xn670kfA9PVd_Wde6UDwDNGE4yRfCsX8wlBhE4o4RIhdgNGOM-LTHLGb8EIISwySQW9Bw8x7obIGSMjEL9SXx9h5-CisSYFb3QDZ1sdtEk2-Ji8idB1Ac573WQrnSwsl2WEG5-2cBqP-709QXBu3YDD-UAEX_XJd22Euq3hGdl04Qcu-9ac94_gzukm2qfrHIPv5aKcvWfrz9XHbLrODGF5ynTlciQ1qjEz2hnBakFIUUkrpSwEx8TVphAVrmvLClxV3ObU2iLXQhTYUU7H4PVy9xC6397GpHZdH9rhpSICSyYl4WhooUvLhC7GYJ06BL_X4agwUie1alCrTmrVVe2AvFwQb639V8eYcYrpH1hRdc4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2819499260</pqid></control><display><type>article</type><title>Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions</title><source>IEEE Electronic Library (IEL)</source><creator>Hsu, Chih-Chieh ; Li, Jin-Xian ; Huang, Po-Cheng ; Jhang, Wun-Ciang ; Joodaki, Mojtaba</creator><creatorcontrib>Hsu, Chih-Chieh ; Li, Jin-Xian ; Huang, Po-Cheng ; Jhang, Wun-Ciang ; Joodaki, Mojtaba</creatorcontrib><description>Combined effects of asymmetric defect distributions and asymmetric gate work functions (WFs) on the performances of self-aligned dual-gate poly-Si TFTs are investigated. Normally, small grains with plentiful grain boundaries (GBs) or other structural defects appear at different positions of the poly-Si film, which is dependent on the growth process of the film. Subgap states of acceptor-like tail, acceptor-like deep-level, donor-like tail, and donor-like deep-level states are used to emulate the defects. Two sets of density of states (DOS) are employed. We find that defects at different positions of the source-side and drain-side channels exhibit different influences on TFT performance and the influences are dependent on the WFs of the gates. TFTs with a higher gate WF can have a higher tolerance to the depth of the defect region. Besides the electrical characteristics, the combined effects of defects and gate WFs on current density distributions and electric field distributions in the channel regions are explored. The performance variations caused by the asymmetric defects along with asymmetric gate WFs can be explained.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2023.3269004</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Crystal defects ; Current density ; Defects ; Degradation ; Density of states ; dual gates ; Electric fields ; Electric variables ; electrical characteristics ; Grain boundaries ; Indexes ; Logic gates ; polycrystalline silicon ; Polysilicon ; Self alignment ; Silicon films ; Skewed distributions ; Tail ; technology computer-aided design (TCAD) simulation ; Thin film transistors ; thin-film transistor (TFT) ; Work functions</subject><ispartof>IEEE transactions on electron devices, 2023-06, Vol.70 (6), p.1-4</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c245t-abf509a0d14cafc84d8227b9e99978612fdc78b1dde471bb6e53ee75a8871f363</cites><orcidid>0000-0002-1007-5079 ; 0000-0002-2239-1271 ; 0000-0002-3032-4546</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10114631$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10114631$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hsu, Chih-Chieh</creatorcontrib><creatorcontrib>Li, Jin-Xian</creatorcontrib><creatorcontrib>Huang, Po-Cheng</creatorcontrib><creatorcontrib>Jhang, Wun-Ciang</creatorcontrib><creatorcontrib>Joodaki, Mojtaba</creatorcontrib><title>Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>Combined effects of asymmetric defect distributions and asymmetric gate work functions (WFs) on the performances of self-aligned dual-gate poly-Si TFTs are investigated. Normally, small grains with plentiful grain boundaries (GBs) or other structural defects appear at different positions of the poly-Si film, which is dependent on the growth process of the film. Subgap states of acceptor-like tail, acceptor-like deep-level, donor-like tail, and donor-like deep-level states are used to emulate the defects. Two sets of density of states (DOS) are employed. We find that defects at different positions of the source-side and drain-side channels exhibit different influences on TFT performance and the influences are dependent on the WFs of the gates. TFTs with a higher gate WF can have a higher tolerance to the depth of the defect region. Besides the electrical characteristics, the combined effects of defects and gate WFs on current density distributions and electric field distributions in the channel regions are explored. The performance variations caused by the asymmetric defects along with asymmetric gate WFs can be explained.</description><subject>Crystal defects</subject><subject>Current density</subject><subject>Defects</subject><subject>Degradation</subject><subject>Density of states</subject><subject>dual gates</subject><subject>Electric fields</subject><subject>Electric variables</subject><subject>electrical characteristics</subject><subject>Grain boundaries</subject><subject>Indexes</subject><subject>Logic gates</subject><subject>polycrystalline silicon</subject><subject>Polysilicon</subject><subject>Self alignment</subject><subject>Silicon films</subject><subject>Skewed distributions</subject><subject>Tail</subject><subject>technology computer-aided design (TCAD) simulation</subject><subject>Thin film transistors</subject><subject>thin-film transistor (TFT)</subject><subject>Work functions</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkDtPwzAURi0EEqWwMzBYYk7xK449Vn2BVImBoI6W49iqS5oU2xn670kfA9PVd_Wde6UDwDNGE4yRfCsX8wlBhE4o4RIhdgNGOM-LTHLGb8EIISwySQW9Bw8x7obIGSMjEL9SXx9h5-CisSYFb3QDZ1sdtEk2-Ji8idB1Ac573WQrnSwsl2WEG5-2cBqP-709QXBu3YDD-UAEX_XJd22Euq3hGdl04Qcu-9ac94_gzukm2qfrHIPv5aKcvWfrz9XHbLrODGF5ynTlciQ1qjEz2hnBakFIUUkrpSwEx8TVphAVrmvLClxV3ObU2iLXQhTYUU7H4PVy9xC6397GpHZdH9rhpSICSyYl4WhooUvLhC7GYJ06BL_X4agwUie1alCrTmrVVe2AvFwQb639V8eYcYrpH1hRdc4</recordid><startdate>20230601</startdate><enddate>20230601</enddate><creator>Hsu, Chih-Chieh</creator><creator>Li, Jin-Xian</creator><creator>Huang, Po-Cheng</creator><creator>Jhang, Wun-Ciang</creator><creator>Joodaki, Mojtaba</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-1007-5079</orcidid><orcidid>https://orcid.org/0000-0002-2239-1271</orcidid><orcidid>https://orcid.org/0000-0002-3032-4546</orcidid></search><sort><creationdate>20230601</creationdate><title>Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions</title><author>Hsu, Chih-Chieh ; Li, Jin-Xian ; Huang, Po-Cheng ; Jhang, Wun-Ciang ; Joodaki, Mojtaba</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c245t-abf509a0d14cafc84d8227b9e99978612fdc78b1dde471bb6e53ee75a8871f363</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Crystal defects</topic><topic>Current density</topic><topic>Defects</topic><topic>Degradation</topic><topic>Density of states</topic><topic>dual gates</topic><topic>Electric fields</topic><topic>Electric variables</topic><topic>electrical characteristics</topic><topic>Grain boundaries</topic><topic>Indexes</topic><topic>Logic gates</topic><topic>polycrystalline silicon</topic><topic>Polysilicon</topic><topic>Self alignment</topic><topic>Silicon films</topic><topic>Skewed distributions</topic><topic>Tail</topic><topic>technology computer-aided design (TCAD) simulation</topic><topic>Thin film transistors</topic><topic>thin-film transistor (TFT)</topic><topic>Work functions</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hsu, Chih-Chieh</creatorcontrib><creatorcontrib>Li, Jin-Xian</creatorcontrib><creatorcontrib>Huang, Po-Cheng</creatorcontrib><creatorcontrib>Jhang, Wun-Ciang</creatorcontrib><creatorcontrib>Joodaki, Mojtaba</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hsu, Chih-Chieh</au><au>Li, Jin-Xian</au><au>Huang, Po-Cheng</au><au>Jhang, Wun-Ciang</au><au>Joodaki, Mojtaba</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2023-06-01</date><risdate>2023</risdate><volume>70</volume><issue>6</issue><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>Combined effects of asymmetric defect distributions and asymmetric gate work functions (WFs) on the performances of self-aligned dual-gate poly-Si TFTs are investigated. Normally, small grains with plentiful grain boundaries (GBs) or other structural defects appear at different positions of the poly-Si film, which is dependent on the growth process of the film. Subgap states of acceptor-like tail, acceptor-like deep-level, donor-like tail, and donor-like deep-level states are used to emulate the defects. Two sets of density of states (DOS) are employed. We find that defects at different positions of the source-side and drain-side channels exhibit different influences on TFT performance and the influences are dependent on the WFs of the gates. TFTs with a higher gate WF can have a higher tolerance to the depth of the defect region. Besides the electrical characteristics, the combined effects of defects and gate WFs on current density distributions and electric field distributions in the channel regions are explored. The performance variations caused by the asymmetric defects along with asymmetric gate WFs can be explained.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2023.3269004</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-1007-5079</orcidid><orcidid>https://orcid.org/0000-0002-2239-1271</orcidid><orcidid>https://orcid.org/0000-0002-3032-4546</orcidid></addata></record> |
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| subjects | Crystal defects Current density Defects Degradation Density of states dual gates Electric fields Electric variables electrical characteristics Grain boundaries Indexes Logic gates polycrystalline silicon Polysilicon Self alignment Silicon films Skewed distributions Tail technology computer-aided design (TCAD) simulation Thin film transistors thin-film transistor (TFT) Work functions |
| title | Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions |
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