Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors
In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically throug...
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| Veröffentlicht in: | IEEE transactions on electron devices 2020-09, Vol.67 (9), p.1-5 |
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| container_title | IEEE transactions on electron devices |
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| creator | Lin, Chih-Chih Tai, Mao-Chou Chang, Ting-Chang Tsao, Yu-Ching Wang, Yu-Xuan Tsai, Yu-Lin Tu, Hong-Yi Lu, I-Nien Tsai, Tsung-Ming Huang, Jen-Wei |
| description | In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control. |
| doi_str_mv | 10.1109/TED.2020.3011386 |
| format | Article |
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A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2020.3011386</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Amorphous InGaZnO (a-IGZO) ; channel thickness ; charge trapping ; Depletion ; Electrons ; Indium gallium zinc oxide ; interface defects ; Logic gates ; Mathematical model ; Reliability ; Semiconductor devices ; Shielding ; Stress ; Thin film transistors ; Thin films ; Threshold voltage ; Trapping</subject><ispartof>IEEE transactions on electron devices, 2020-09, Vol.67 (9), p.1-5</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-21f666989fee706a48315da2f697dfaeef5cbc964f0b61b0dae4ba3f6f02c7e63</citedby><cites>FETCH-LOGICAL-c291t-21f666989fee706a48315da2f697dfaeef5cbc964f0b61b0dae4ba3f6f02c7e63</cites><orcidid>0000-0002-8840-6763 ; 0000-0002-5301-6693 ; 0000-0002-2106-691X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9159893$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9159893$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lin, Chih-Chih</creatorcontrib><creatorcontrib>Tai, Mao-Chou</creatorcontrib><creatorcontrib>Chang, Ting-Chang</creatorcontrib><creatorcontrib>Tsao, Yu-Ching</creatorcontrib><creatorcontrib>Wang, Yu-Xuan</creatorcontrib><creatorcontrib>Tsai, Yu-Lin</creatorcontrib><creatorcontrib>Tu, Hong-Yi</creatorcontrib><creatorcontrib>Lu, I-Nien</creatorcontrib><creatorcontrib>Tsai, Tsung-Ming</creatorcontrib><creatorcontrib>Huang, Jen-Wei</creatorcontrib><title>Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.</description><subject>Amorphous InGaZnO (a-IGZO)</subject><subject>channel thickness</subject><subject>charge trapping</subject><subject>Depletion</subject><subject>Electrons</subject><subject>Indium gallium zinc oxide</subject><subject>interface defects</subject><subject>Logic gates</subject><subject>Mathematical model</subject><subject>Reliability</subject><subject>Semiconductor devices</subject><subject>Shielding</subject><subject>Stress</subject><subject>Thin film transistors</subject><subject>Thin films</subject><subject>Threshold voltage</subject><subject>Trapping</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9UE1Lw0AUXETBWr0LXgKeU_crm-xR-mWhUNB48bJskrd2S7qJu-nBf--GFk-PmTfz3jAIPRI8IwTLl3K5mFFM8YxhQlghrtCEZFmeSsHFNZpgTIpUsoLdorsQDhEKzukEvW_cAN7oGpIFGKiH5GNvoW2s-046kyzbSPnOJaXXfT-S1iU63bi1_nK7pNxHuLLtcdy7YMPQ-XCPboxuAzxc5hR9rpbl_C3d7tab-es2rakkQ0qJEULIQhqAHAvNC0ayRlMjZN4YDWCyuqpjfIMrQSrcaOCVZkYYTOscBJui5_Pd3nc_JwiDOnQn7-JLRTkTHGdMsKjCZ1XtuxA8GNV7e9T-VxGsxuZUbE6NzalLc9HydLZYAPiXS5LFsIz9AbxkaYg</recordid><startdate>20200901</startdate><enddate>20200901</enddate><creator>Lin, Chih-Chih</creator><creator>Tai, Mao-Chou</creator><creator>Chang, Ting-Chang</creator><creator>Tsao, Yu-Ching</creator><creator>Wang, Yu-Xuan</creator><creator>Tsai, Yu-Lin</creator><creator>Tu, Hong-Yi</creator><creator>Lu, I-Nien</creator><creator>Tsai, Tsung-Ming</creator><creator>Huang, Jen-Wei</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-8840-6763</orcidid><orcidid>https://orcid.org/0000-0002-5301-6693</orcidid><orcidid>https://orcid.org/0000-0002-2106-691X</orcidid></search><sort><creationdate>20200901</creationdate><title>Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors</title><author>Lin, Chih-Chih ; Tai, Mao-Chou ; Chang, Ting-Chang ; Tsao, Yu-Ching ; Wang, Yu-Xuan ; Tsai, Yu-Lin ; Tu, Hong-Yi ; Lu, I-Nien ; Tsai, Tsung-Ming ; Huang, Jen-Wei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-21f666989fee706a48315da2f697dfaeef5cbc964f0b61b0dae4ba3f6f02c7e63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Amorphous InGaZnO (a-IGZO)</topic><topic>channel thickness</topic><topic>charge trapping</topic><topic>Depletion</topic><topic>Electrons</topic><topic>Indium gallium zinc oxide</topic><topic>interface defects</topic><topic>Logic gates</topic><topic>Mathematical model</topic><topic>Reliability</topic><topic>Semiconductor devices</topic><topic>Shielding</topic><topic>Stress</topic><topic>Thin film transistors</topic><topic>Thin films</topic><topic>Threshold voltage</topic><topic>Trapping</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lin, Chih-Chih</creatorcontrib><creatorcontrib>Tai, Mao-Chou</creatorcontrib><creatorcontrib>Chang, Ting-Chang</creatorcontrib><creatorcontrib>Tsao, Yu-Ching</creatorcontrib><creatorcontrib>Wang, Yu-Xuan</creatorcontrib><creatorcontrib>Tsai, Yu-Lin</creatorcontrib><creatorcontrib>Tu, Hong-Yi</creatorcontrib><creatorcontrib>Lu, I-Nien</creatorcontrib><creatorcontrib>Tsai, Tsung-Ming</creatorcontrib><creatorcontrib>Huang, Jen-Wei</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lin, Chih-Chih</au><au>Tai, Mao-Chou</au><au>Chang, Ting-Chang</au><au>Tsao, Yu-Ching</au><au>Wang, Yu-Xuan</au><au>Tsai, Yu-Lin</au><au>Tu, Hong-Yi</au><au>Lu, I-Nien</au><au>Tsai, Tsung-Ming</au><au>Huang, Jen-Wei</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2020-09-01</date><risdate>2020</risdate><volume>67</volume><issue>9</issue><spage>1</spage><epage>5</epage><pages>1-5</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2020.3011386</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-8840-6763</orcidid><orcidid>https://orcid.org/0000-0002-5301-6693</orcidid><orcidid>https://orcid.org/0000-0002-2106-691X</orcidid></addata></record> |
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| subjects | Amorphous InGaZnO (a-IGZO) channel thickness charge trapping Depletion Electrons Indium gallium zinc oxide interface defects Logic gates Mathematical model Reliability Semiconductor devices Shielding Stress Thin film transistors Thin films Threshold voltage Trapping |
| title | Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors |
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