Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme
In this work, we report two performance enhancement schemes for single-gate vertical-channel (SGVC) 3-D NAND Flash. The first one features a programming (PGM) waveform where the bias of the dummy wordline (DWL) is raised in a two-step manner so that the resultant disturbance that the DWL and edge WL...
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| Veröffentlicht in: | IEEE transactions on electron devices 2020-01, Vol.67 (1), p.99-104 |
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| container_title | IEEE transactions on electron devices |
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| creator | Chen, Wei-Chen Lue, Hang-Ting Hsieh, Chih-Chang Wang, Keh-Chung Lu, Chih-Yuan |
| description | In this work, we report two performance enhancement schemes for single-gate vertical-channel (SGVC) 3-D NAND Flash. The first one features a programming (PGM) waveform where the bias of the dummy wordline (DWL) is raised in a two-step manner so that the resultant disturbance that the DWL and edge WL suffer is appreciably alleviated. The second scheme takes advantage of a unique behavior termed "self-boosting-enhanced-PGM" mechanism in the pair- bitline PGM method to deal with the slow PGM bits and achieve a much lower bit error rate as a consequence. By using these two approaches, the bit error rate after multilevel cell (MLC) operation can be substantially improved by 82%. |
| doi_str_mv | 10.1109/TED.2019.2951460 |
| format | Article |
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By using these two approaches, the bit error rate after multilevel cell (MLC) operation can be substantially improved by 82%.</description><subject>3-D NAND</subject><subject>Bit error rate</subject><subject>Computer architecture</subject><subject>disturbance</subject><subject>dummy wordline (DWL)</subject><subject>Erbium</subject><subject>flash</subject><subject>Flash memories</subject><subject>hot carrier</subject><subject>Hot carrier effects</subject><subject>Logic gates</subject><subject>Microprocessors</subject><subject>pair bitline (BL)</subject><subject>Performance enhancement</subject><subject>polycrystalline silicon</subject><subject>thin film transistor</subject><subject>two-step waveform</subject><subject>Waveforms</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpVkM1Lw0AUxBdRsFbvgpcFz6n7lY891qZVodRCKz0u2-Rtm9Jk6yZRevFvd0OL4Gl4j9_MwCB0T8mAUiKfluN0wAiVAyZDKiJygXo0DONARiK6RD1CaBJInvBrdFPXO39GQrAe-pmDM9aVusoAj6ttpyVUDbYG8yDFs-EsxZO9rrd4ArppXVFtsMbLbxssGjjgtC3LI15Zl--LCvDc2Y3TJV7pL-hisa5yPNeFC56L5h-xyLa-6BZdGb2v4e6sffQxGS9Hr8H0_eVtNJwGGZO0CXQsw4xIKZKI8JhxI4WIgeTAWcySXAAIYvzHkCjJiMm1FOu1pEkWGp1LCbyPHk-5B2c_W6gbtbOtq3ylYpzzULAojj1FTlTmbF07MOrgilK7o6JEdSsrv7LqVlbnlb3l4WQpAOAPT6SHCOe_vKp3wQ</recordid><startdate>202001</startdate><enddate>202001</enddate><creator>Chen, Wei-Chen</creator><creator>Lue, Hang-Ting</creator><creator>Hsieh, Chih-Chang</creator><creator>Wang, Keh-Chung</creator><creator>Lu, Chih-Yuan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| ispartof | IEEE transactions on electron devices, 2020-01, Vol.67 (1), p.99-104 |
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| source | IEEE Electronic Library (IEL) |
| subjects | 3-D NAND Bit error rate Computer architecture disturbance dummy wordline (DWL) Erbium flash Flash memories hot carrier Hot carrier effects Logic gates Microprocessors pair bitline (BL) Performance enhancement polycrystalline silicon thin film transistor two-step waveform Waveforms |
| title | Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme |
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