Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices

Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanis...

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Veröffentlicht in:IEEE transactions on electron devices 2019-03, Vol.66 (3), p.1145-1152
Hauptverfasser: Medina-Bailon, Cristina, Padilla, Jose L., Sadi, Toufik, Sampedro, Carlos, Godoy, Andres, Donetti, Luca, Georgiev, Vihar P., Gamiz, Francisco, Asenov, Asen
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container_issue 3
container_start_page 1145
container_title IEEE transactions on electron devices
container_volume 66
creator Medina-Bailon, Cristina
Padilla, Jose L.
Sadi, Toufik
Sampedro, Carlos
Godoy, Andres
Donetti, Luca
Georgiev, Vihar P.
Gamiz, Francisco
Asenov, Asen
description Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths.
doi_str_mv 10.1109/TED.2019.2890985
format Article
fullrecord <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TED_2019_2890985</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8618336</ieee_id><sourcerecordid>2185732295</sourcerecordid><originalsourceid>FETCH-LOGICAL-c333t-362362eb8c47a0dc8b21ff913385adbf83f4f8ba775539e2f32bb7370c330d503</originalsourceid><addsrcrecordid>eNo9kM1LxDAQxYMouH7cBS8Br3ZNMk2bHGU_VFjx4HouSTvRaDfVphX0rzfrijDwGOa9B_Mj5IyzKedMX60X86lgXE-F0kwruUcmXMoy00Ve7JMJY1xlGhQckqMYX9Na5LmYkO_7sR18HK01oaGLEHFjW6T3XRiQzkzfdvQ6mPYr-kg7R9djCNj68ExXaN7Mc3Ji_WKCj5tIfaBP7dCbWJsWG7qcPz7cXdL5za9s65c-LBdrOsdPX2M8IQfOtBFP__SYPKXr7DZbPdzcza5XWQ0AQwaFSINW1XlpWFMrK7hzmgMoaRrrFLjcKWvKUkrQKBwIa0soWYqzRjI4Jhe73ve--xgxDtVrN_bpqVgJrmQJQmiZXGznqvsuxh5d9d77jem_Ks6qLeEqEa62hKs_wilyvot4RPy3q4IrgAJ-AMXkdew</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2185732295</pqid></control><display><type>article</type><title>Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices</title><source>IEEE Electronic Library (IEL)</source><creator>Medina-Bailon, Cristina ; Padilla, Jose L. ; Sadi, Toufik ; Sampedro, Carlos ; Godoy, Andres ; Donetti, Luca ; Georgiev, Vihar P. ; Gamiz, Francisco ; Asenov, Asen</creator><creatorcontrib>Medina-Bailon, Cristina ; Padilla, Jose L. ; Sadi, Toufik ; Sampedro, Carlos ; Godoy, Andres ; Donetti, Luca ; Georgiev, Vihar P. ; Gamiz, Francisco ; Asenov, Asen</creatorcontrib><description>Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2019.2890985</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Band-to-band tunneling (BTBT) ; Computer simulation ; Current leakage ; Devices ; direct source-to-drain tunneling (S/D tunneling) ; double-gate silicon on insulator (DGSOI) ; Electric potential ; Electron traps ; FinFET ; FinFETs ; fully depleted silicon on insulator (FDSOI) ; gate leakage current ; Gates ; Logic gates ; Monte Carlo methods ; multissubband ensemble Monte Carlo (MS-EMC) ; Nanoelectronics ; Nanotechnology devices ; Silicon ; Silicon-on-insulator ; Simulators ; Tunneling</subject><ispartof>IEEE transactions on electron devices, 2019-03, Vol.66 (3), p.1145-1152</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c333t-362362eb8c47a0dc8b21ff913385adbf83f4f8ba775539e2f32bb7370c330d503</citedby><cites>FETCH-LOGICAL-c333t-362362eb8c47a0dc8b21ff913385adbf83f4f8ba775539e2f32bb7370c330d503</cites><orcidid>0000-0002-2082-5304 ; 0000-0003-1451-5163 ; 0000-0001-8730-2594 ; 0000-0002-3014-8765 ; 0000-0001-6473-2508 ; 0000-0002-5072-7924 ; 0000-0002-4280-3149 ; 0000-0002-5189-867X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8618336$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8618336$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Medina-Bailon, Cristina</creatorcontrib><creatorcontrib>Padilla, Jose L.</creatorcontrib><creatorcontrib>Sadi, Toufik</creatorcontrib><creatorcontrib>Sampedro, Carlos</creatorcontrib><creatorcontrib>Godoy, Andres</creatorcontrib><creatorcontrib>Donetti, Luca</creatorcontrib><creatorcontrib>Georgiev, Vihar P.</creatorcontrib><creatorcontrib>Gamiz, Francisco</creatorcontrib><creatorcontrib>Asenov, Asen</creatorcontrib><title>Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths.</description><subject>Band-to-band tunneling (BTBT)</subject><subject>Computer simulation</subject><subject>Current leakage</subject><subject>Devices</subject><subject>direct source-to-drain tunneling (S/D tunneling)</subject><subject>double-gate silicon on insulator (DGSOI)</subject><subject>Electric potential</subject><subject>Electron traps</subject><subject>FinFET</subject><subject>FinFETs</subject><subject>fully depleted silicon on insulator (FDSOI)</subject><subject>gate leakage current</subject><subject>Gates</subject><subject>Logic gates</subject><subject>Monte Carlo methods</subject><subject>multissubband ensemble Monte Carlo (MS-EMC)</subject><subject>Nanoelectronics</subject><subject>Nanotechnology devices</subject><subject>Silicon</subject><subject>Silicon-on-insulator</subject><subject>Simulators</subject><subject>Tunneling</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1LxDAQxYMouH7cBS8Br3ZNMk2bHGU_VFjx4HouSTvRaDfVphX0rzfrijDwGOa9B_Mj5IyzKedMX60X86lgXE-F0kwruUcmXMoy00Ve7JMJY1xlGhQckqMYX9Na5LmYkO_7sR18HK01oaGLEHFjW6T3XRiQzkzfdvQ6mPYr-kg7R9djCNj68ExXaN7Mc3Ji_WKCj5tIfaBP7dCbWJsWG7qcPz7cXdL5za9s65c-LBdrOsdPX2M8IQfOtBFP__SYPKXr7DZbPdzcza5XWQ0AQwaFSINW1XlpWFMrK7hzmgMoaRrrFLjcKWvKUkrQKBwIa0soWYqzRjI4Jhe73ve--xgxDtVrN_bpqVgJrmQJQmiZXGznqvsuxh5d9d77jem_Ks6qLeEqEa62hKs_wilyvot4RPy3q4IrgAJ-AMXkdew</recordid><startdate>20190301</startdate><enddate>20190301</enddate><creator>Medina-Bailon, Cristina</creator><creator>Padilla, Jose L.</creator><creator>Sadi, Toufik</creator><creator>Sampedro, Carlos</creator><creator>Godoy, Andres</creator><creator>Donetti, Luca</creator><creator>Georgiev, Vihar P.</creator><creator>Gamiz, Francisco</creator><creator>Asenov, Asen</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-2082-5304</orcidid><orcidid>https://orcid.org/0000-0003-1451-5163</orcidid><orcidid>https://orcid.org/0000-0001-8730-2594</orcidid><orcidid>https://orcid.org/0000-0002-3014-8765</orcidid><orcidid>https://orcid.org/0000-0001-6473-2508</orcidid><orcidid>https://orcid.org/0000-0002-5072-7924</orcidid><orcidid>https://orcid.org/0000-0002-4280-3149</orcidid><orcidid>https://orcid.org/0000-0002-5189-867X</orcidid></search><sort><creationdate>20190301</creationdate><title>Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices</title><author>Medina-Bailon, Cristina ; Padilla, Jose L. ; Sadi, Toufik ; Sampedro, Carlos ; Godoy, Andres ; Donetti, Luca ; Georgiev, Vihar P. ; Gamiz, Francisco ; Asenov, Asen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c333t-362362eb8c47a0dc8b21ff913385adbf83f4f8ba775539e2f32bb7370c330d503</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Band-to-band tunneling (BTBT)</topic><topic>Computer simulation</topic><topic>Current leakage</topic><topic>Devices</topic><topic>direct source-to-drain tunneling (S/D tunneling)</topic><topic>double-gate silicon on insulator (DGSOI)</topic><topic>Electric potential</topic><topic>Electron traps</topic><topic>FinFET</topic><topic>FinFETs</topic><topic>fully depleted silicon on insulator (FDSOI)</topic><topic>gate leakage current</topic><topic>Gates</topic><topic>Logic gates</topic><topic>Monte Carlo methods</topic><topic>multissubband ensemble Monte Carlo (MS-EMC)</topic><topic>Nanoelectronics</topic><topic>Nanotechnology devices</topic><topic>Silicon</topic><topic>Silicon-on-insulator</topic><topic>Simulators</topic><topic>Tunneling</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Medina-Bailon, Cristina</creatorcontrib><creatorcontrib>Padilla, Jose L.</creatorcontrib><creatorcontrib>Sadi, Toufik</creatorcontrib><creatorcontrib>Sampedro, Carlos</creatorcontrib><creatorcontrib>Godoy, Andres</creatorcontrib><creatorcontrib>Donetti, Luca</creatorcontrib><creatorcontrib>Georgiev, Vihar P.</creatorcontrib><creatorcontrib>Gamiz, Francisco</creatorcontrib><creatorcontrib>Asenov, Asen</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Medina-Bailon, Cristina</au><au>Padilla, Jose L.</au><au>Sadi, Toufik</au><au>Sampedro, Carlos</au><au>Godoy, Andres</au><au>Donetti, Luca</au><au>Georgiev, Vihar P.</au><au>Gamiz, Francisco</au><au>Asenov, Asen</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2019-03-01</date><risdate>2019</risdate><volume>66</volume><issue>3</issue><spage>1145</spage><epage>1152</epage><pages>1145-1152</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2019.2890985</doi><tpages>8</tpages><orcidid>https://orcid.org/0000-0002-2082-5304</orcidid><orcidid>https://orcid.org/0000-0003-1451-5163</orcidid><orcidid>https://orcid.org/0000-0001-8730-2594</orcidid><orcidid>https://orcid.org/0000-0002-3014-8765</orcidid><orcidid>https://orcid.org/0000-0001-6473-2508</orcidid><orcidid>https://orcid.org/0000-0002-5072-7924</orcidid><orcidid>https://orcid.org/0000-0002-4280-3149</orcidid><orcidid>https://orcid.org/0000-0002-5189-867X</orcidid><oa>free_for_read</oa></addata></record>
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1557-9646
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subjects Band-to-band tunneling (BTBT)
Computer simulation
Current leakage
Devices
direct source-to-drain tunneling (S/D tunneling)
double-gate silicon on insulator (DGSOI)
Electric potential
Electron traps
FinFET
FinFETs
fully depleted silicon on insulator (FDSOI)
gate leakage current
Gates
Logic gates
Monte Carlo methods
multissubband ensemble Monte Carlo (MS-EMC)
Nanoelectronics
Nanotechnology devices
Silicon
Silicon-on-insulator
Simulators
Tunneling
title Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T02%3A23%3A34IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Multisubband%20Ensemble%20Monte%20Carlo%20Analysis%20of%20Tunneling%20Leakage%20Mechanisms%20in%20Ultrascaled%20FDSOI,%20DGSOI,%20and%20FinFET%20Devices&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Medina-Bailon,%20Cristina&rft.date=2019-03-01&rft.volume=66&rft.issue=3&rft.spage=1145&rft.epage=1152&rft.pages=1145-1152&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2019.2890985&rft_dat=%3Cproquest_RIE%3E2185732295%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2185732295&rft_id=info:pmid/&rft_ieee_id=8618336&rfr_iscdi=true