Estimation of Threshold Voltage in SiC Short-Channel MOSFETs

In this brief, the influence of high-density traps at the SiO 2 /SiC interface on short-channel effects was investigated, and a model describing channel length dependence of the threshold voltage (i.e., the gate voltage at a given drain current) is proposed. First, we determined the densities of int...

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Veröffentlicht in:	IEEE transactions on electron devices 2018-07, Vol.65 (7), p.3077-3080
Hauptverfasser:	Tachiki, Keita, Ono, Takahisa, Kobayashi, Takuma, Tanaka, Hajime, Kimoto, Tsunenobu
Format:	Artikel
Sprache:	eng
Schlagworte:	Electron traps Interface state density (Dit) Interface states Logic gates MOS MOSFETs Semiconductor device modeling short-channel effect (SCE) Silicon carbide silicon carbide (SiC) Threshold voltage
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