Side-by-Side Comparison of Single- and Dual-Active Layer Oxide TFTs: Experiment and TCAD Simulation
Single-active layer (SAL) and dual-active layer (DAL) oxide thin-film transistors (TFTs) are fabricated using the same process conditions and compared side by side. The SAL channel consists of amorphous In-Ga-Zn-O (a-IGZO), and the DAL of ultrathin In-Sn-O and a-IGZO. The DAL TFT exhibits strongly i...
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| Veröffentlicht in: | IEEE transactions on electron devices 2017-10, Vol.64 (10), p.4131-4136 |
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| container_title | IEEE transactions on electron devices |
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| creator | Stewart, Kevin A. Gouliouk, Vasily McGlone, John M. Wager, John F. |
| description | Single-active layer (SAL) and dual-active layer (DAL) oxide thin-film transistors (TFTs) are fabricated using the same process conditions and compared side by side. The SAL channel consists of amorphous In-Ga-Zn-O (a-IGZO), and the DAL of ultrathin In-Sn-O and a-IGZO. The DAL TFT exhibits strongly improved performance compared to the SAL TFT such as higher mobility of 31 cm 2 ·V -1 ·s -1 , smaller subthreshold swing of 175 mV/dec, and better positive bias temperature stress stability. Technology computeraided design simulation is used to investigate the SAL and DAL device performance. A mapping technique is used to directly correlate the transfer characteristics to the subbandgap density of states. The simulation suggests that the improved performance of the DAL TFT is due to an improved gate insulator/channel interface with an approximately one order of magnitude lower interface trap density. |
| doi_str_mv | 10.1109/TED.2017.2743062 |
| format | Article |
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The SAL channel consists of amorphous In-Ga-Zn-O (a-IGZO), and the DAL of ultrathin In-Sn-O and a-IGZO. The DAL TFT exhibits strongly improved performance compared to the SAL TFT such as higher mobility of 31 cm 2 ·V -1 ·s -1 , smaller subthreshold swing of 175 mV/dec, and better positive bias temperature stress stability. Technology computeraided design simulation is used to investigate the SAL and DAL device performance. A mapping technique is used to directly correlate the transfer characteristics to the subbandgap density of states. The simulation suggests that the improved performance of the DAL TFT is due to an improved gate insulator/channel interface with an approximately one order of magnitude lower interface trap density.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2017.2743062</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>CAD ; Computational modeling ; Computer aided design ; Computer simulation ; Dual-active layer (DAL) ; high mobility ; Indium tin oxide ; In–Ga–Zn–O (IGZO) ; In–Sn–O (ITO) ; Logic gates ; Performance evaluation ; Semiconductor devices ; Simulation ; Stress ; technology computeraided design (TCAD) simulation ; Thin film transistors ; thin-film transistor (TFT) ; Threshold voltage</subject><ispartof>IEEE transactions on electron devices, 2017-10, Vol.64 (10), p.4131-4136</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c357t-1a1df7f58e1318b75472ca95520e259237abc16026cc22a73373bfa382936303</citedby><cites>FETCH-LOGICAL-c357t-1a1df7f58e1318b75472ca95520e259237abc16026cc22a73373bfa382936303</cites><orcidid>0000-0001-6065-7213</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8019888$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8019888$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Stewart, Kevin A.</creatorcontrib><creatorcontrib>Gouliouk, Vasily</creatorcontrib><creatorcontrib>McGlone, John M.</creatorcontrib><creatorcontrib>Wager, John F.</creatorcontrib><title>Side-by-Side Comparison of Single- and Dual-Active Layer Oxide TFTs: Experiment and TCAD Simulation</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>Single-active layer (SAL) and dual-active layer (DAL) oxide thin-film transistors (TFTs) are fabricated using the same process conditions and compared side by side. The SAL channel consists of amorphous In-Ga-Zn-O (a-IGZO), and the DAL of ultrathin In-Sn-O and a-IGZO. The DAL TFT exhibits strongly improved performance compared to the SAL TFT such as higher mobility of 31 cm 2 ·V -1 ·s -1 , smaller subthreshold swing of 175 mV/dec, and better positive bias temperature stress stability. Technology computeraided design simulation is used to investigate the SAL and DAL device performance. A mapping technique is used to directly correlate the transfer characteristics to the subbandgap density of states. The simulation suggests that the improved performance of the DAL TFT is due to an improved gate insulator/channel interface with an approximately one order of magnitude lower interface trap density.</description><subject>CAD</subject><subject>Computational modeling</subject><subject>Computer aided design</subject><subject>Computer simulation</subject><subject>Dual-active layer (DAL)</subject><subject>high mobility</subject><subject>Indium tin oxide</subject><subject>In–Ga–Zn–O (IGZO)</subject><subject>In–Sn–O (ITO)</subject><subject>Logic gates</subject><subject>Performance evaluation</subject><subject>Semiconductor devices</subject><subject>Simulation</subject><subject>Stress</subject><subject>technology computeraided design (TCAD) simulation</subject><subject>Thin film transistors</subject><subject>thin-film transistor (TFT)</subject><subject>Threshold voltage</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM9LwzAUx4MoOKd3wUvAc2aS1zSJt7EfKgx2WO8hzVLp6NqatOL-e1s3PH158Pm89_gi9MjojDGqX7LVcsYpkzMuE6Apv0ITJoQkOk3SazShlCmiQcEtuovxMIxpkvAJcrty70l-ImPiRXNsbShjU-OmwLuy_qw8wbbe42VvKzJ3Xfnt8caefMDbn9HI1ll8xauf1ofy6OvuD84W8-VgH_vKdmVT36ObwlbRP1xyirL1Klu8k8327WMx3xAHQnaEWbYvZCGUZ8BULkUiubNaCE49F5qDtLljKeWpc5xbCSAhLyworiEFClP0fF7bhuar97Ezh6YP9XDRMA1aJywBGCh6plxoYgy-MO3wuQ0nw6gZmzRDk2Zs0lyaHJSns1J67_9xRZlWSsEvaThsSg</recordid><startdate>20171001</startdate><enddate>20171001</enddate><creator>Stewart, Kevin A.</creator><creator>Gouliouk, Vasily</creator><creator>McGlone, John M.</creator><creator>Wager, John F.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-6065-7213</orcidid></search><sort><creationdate>20171001</creationdate><title>Side-by-Side Comparison of Single- and Dual-Active Layer Oxide TFTs: Experiment and TCAD Simulation</title><author>Stewart, Kevin A. ; Gouliouk, Vasily ; McGlone, John M. ; Wager, John F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c357t-1a1df7f58e1318b75472ca95520e259237abc16026cc22a73373bfa382936303</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CAD</topic><topic>Computational modeling</topic><topic>Computer aided design</topic><topic>Computer simulation</topic><topic>Dual-active layer (DAL)</topic><topic>high mobility</topic><topic>Indium tin oxide</topic><topic>In–Ga–Zn–O (IGZO)</topic><topic>In–Sn–O (ITO)</topic><topic>Logic gates</topic><topic>Performance evaluation</topic><topic>Semiconductor devices</topic><topic>Simulation</topic><topic>Stress</topic><topic>technology computeraided design (TCAD) simulation</topic><topic>Thin film transistors</topic><topic>thin-film transistor (TFT)</topic><topic>Threshold voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Stewart, Kevin A.</creatorcontrib><creatorcontrib>Gouliouk, Vasily</creatorcontrib><creatorcontrib>McGlone, John M.</creatorcontrib><creatorcontrib>Wager, John F.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Stewart, Kevin A.</au><au>Gouliouk, Vasily</au><au>McGlone, John M.</au><au>Wager, John F.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Side-by-Side Comparison of Single- and Dual-Active Layer Oxide TFTs: Experiment and TCAD Simulation</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2017-10-01</date><risdate>2017</risdate><volume>64</volume><issue>10</issue><spage>4131</spage><epage>4136</epage><pages>4131-4136</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>Single-active layer (SAL) and dual-active layer (DAL) oxide thin-film transistors (TFTs) are fabricated using the same process conditions and compared side by side. The SAL channel consists of amorphous In-Ga-Zn-O (a-IGZO), and the DAL of ultrathin In-Sn-O and a-IGZO. The DAL TFT exhibits strongly improved performance compared to the SAL TFT such as higher mobility of 31 cm 2 ·V -1 ·s -1 , smaller subthreshold swing of 175 mV/dec, and better positive bias temperature stress stability. Technology computeraided design simulation is used to investigate the SAL and DAL device performance. A mapping technique is used to directly correlate the transfer characteristics to the subbandgap density of states. The simulation suggests that the improved performance of the DAL TFT is due to an improved gate insulator/channel interface with an approximately one order of magnitude lower interface trap density.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2017.2743062</doi><tpages>6</tpages><orcidid>https://orcid.org/0000-0001-6065-7213</orcidid></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | CAD Computational modeling Computer aided design Computer simulation Dual-active layer (DAL) high mobility Indium tin oxide In–Ga–Zn–O (IGZO) In–Sn–O (ITO) Logic gates Performance evaluation Semiconductor devices Simulation Stress technology computeraided design (TCAD) simulation Thin film transistors thin-film transistor (TFT) Threshold voltage |
| title | Side-by-Side Comparison of Single- and Dual-Active Layer Oxide TFTs: Experiment and TCAD Simulation |
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