Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis
A compact scaling length model for tapered Tri-gate fin field-effect transistors (FinFETs) is presented based on a 3-D simulation and an analytic potential model. Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy...
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| Veröffentlicht in: | IEEE transactions on electron devices 2013-09, Vol.60 (9), p.2721-2727 |
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| container_issue | 9 |
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| container_title | IEEE transactions on electron devices |
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| creator | KO, Myung-Dong SOHN, Chang-Woo BAEK, Chang-Ki JEONG, Yoon-Ha |
| description | A compact scaling length model for tapered Tri-gate fin field-effect transistors (FinFETs) is presented based on a 3-D simulation and an analytic potential model. Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poisson's equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter. |
| doi_str_mv | 10.1109/TED.2013.2272789 |
| format | Article |
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Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poisson's equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2013.2272789</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>3-D Poisson's equation ; Applied sciences ; Electronics ; Exact sciences and technology ; FinFETs ; Logic gates ; Mathematical model ; non-Cartesian mesh ; Numerical models ; Poisson equations ; scaling length ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poisson's equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter.</description><subject>3-D Poisson's equation</subject><subject>Applied sciences</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>FinFETs</subject><subject>Logic gates</subject><subject>Mathematical model</subject><subject>non-Cartesian mesh</subject><subject>Numerical models</subject><subject>Poisson equations</subject><subject>scaling length</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>short-channel effects (SCEs)</subject><subject>Silicon</subject><subject>tapered fin</subject><subject>Transistors</subject><subject>tri-gate FinFET</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEtPAjEUhRujiYjuTdx043Kw706XiIAmGBeM60npA6vDDGmHBf_ekiGs7uuck5sPgEeMJhgj9VLN3yYEYTohRBJZqiswwpzLQgkmrsEIIVwWipb0Ftyl9JtHwRgZgb91f7BH2LVQw7XRTWi3cOXabf8DPzvrGui7CCu9d9FZWMVQLHXv4CK0i3kFX3XK2-ylxRtch92h0X04RbUWTlvdHPuQI4c2hXQPbrxukns41zH4zimz92L1tfyYTVeFoVz1xUYRx4g3wpSUGieFd4Jqbx1nRAjCkBbObBDhnhuGOSHKeGs1U9wShrWkY4CGXBO7lKLz9T6GnY7HGqP6BKvOsOoTrPoMK1ueB8tep_yyj7o1IV18RAopqeJZ9zTognPuchZcCEQ5_QddbXHV</recordid><startdate>20130901</startdate><enddate>20130901</enddate><creator>KO, Myung-Dong</creator><creator>SOHN, Chang-Woo</creator><creator>BAEK, Chang-Ki</creator><creator>JEONG, Yoon-Ha</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20130901</creationdate><title>Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis</title><author>KO, Myung-Dong ; SOHN, Chang-Woo ; BAEK, Chang-Ki ; JEONG, Yoon-Ha</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-b92e42fc6c833ce76fe63afde54266240a6ecb025f5c415229cfdda495d241a73</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>3-D Poisson's equation</topic><topic>Applied sciences</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>FinFETs</topic><topic>Logic gates</topic><topic>Mathematical model</topic><topic>non-Cartesian mesh</topic><topic>Numerical models</topic><topic>Poisson equations</topic><topic>scaling length</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>short-channel effects (SCEs)</topic><topic>Silicon</topic><topic>tapered fin</topic><topic>Transistors</topic><topic>tri-gate FinFET</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>KO, Myung-Dong</creatorcontrib><creatorcontrib>SOHN, Chang-Woo</creatorcontrib><creatorcontrib>BAEK, Chang-Ki</creatorcontrib><creatorcontrib>JEONG, Yoon-Ha</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KO, Myung-Dong</au><au>SOHN, Chang-Woo</au><au>BAEK, Chang-Ki</au><au>JEONG, Yoon-Ha</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2013-09-01</date><risdate>2013</risdate><volume>60</volume><issue>9</issue><spage>2721</spage><epage>2727</epage><pages>2721-2727</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>A compact scaling length model for tapered Tri-gate fin field-effect transistors (FinFETs) is presented based on a 3-D simulation and an analytic potential model. Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poisson's equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2013.2272789</doi><tpages>7</tpages></addata></record> |
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| ispartof | IEEE transactions on electron devices, 2013-09, Vol.60 (9), p.2721-2727 |
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| source | IEEE Electronic Library (IEL) |
| subjects | 3-D Poisson's equation Applied sciences Electronics Exact sciences and technology FinFETs Logic gates Mathematical model non-Cartesian mesh Numerical models Poisson equations scaling length Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices short-channel effects (SCEs) Silicon tapered fin Transistors tri-gate FinFET |
| title | Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis |
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