Modified Potential Well Formed by \hbox/ \hbox/\hbox/\hbox for Flash Memory Application
This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO 2 /SiO x ,Na-TiO x ,N y tunnel barrier, a trap-rich TiO 2 trapping layer, and an abrupt SiO 2 block barrier. The transitional tunnel barrier shrinks to enhanc...
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| Veröffentlicht in: | IEEE transactions on electron devices 2010-11, Vol.57 (11), p.2794-2800 |
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| container_issue | 11 |
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| container_title | IEEE transactions on electron devices |
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| creator | Zhang, Gang Ra, Chang Ho Li, Hua-Min Shen, Tian-zi Cheong, Byung-ki Yoo, Won Jong |
| description | This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO 2 /SiO x ,Na-TiO x ,N y tunnel barrier, a trap-rich TiO 2 trapping layer, and an abrupt SiO 2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N 2 + O 2 thermal treatment, and the TiO 2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming ( 10 6 P/E cycles), large threshold voltage window (ΔV th =M> V), as well as improved data retention at 125 °C. |
| doi_str_mv | 10.1109/TED.2010.2066200 |
| format | Article |
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The MW was formed by using a transitional SiO 2 /SiO x ,Na-TiO x ,N y tunnel barrier, a trap-rich TiO 2 trapping layer, and an abrupt SiO 2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N 2 + O 2 thermal treatment, and the TiO 2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (<; μs) at low-voltage operation (7-10 MV/cm), good P/E endurance (> 10 6 P/E cycles), large threshold voltage window (ΔV th =M> V), as well as improved data retention at 125 °C.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2010.2066200</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>IEEE</publisher><subject>Electron traps ; Flash memory ; hbox{TiO}_{2} trapping layer ; modified engineered-potential-well (MW) ; Silicon ; Tin ; Transient analysis</subject><ispartof>IEEE transactions on electron devices, 2010-11, Vol.57 (11), p.2794-2800</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c1084-dce1a3a1349f0fd52c9305085cc6d3e76cd68a2729734b6bf6a55121965db0cc3</citedby><cites>FETCH-LOGICAL-c1084-dce1a3a1349f0fd52c9305085cc6d3e76cd68a2729734b6bf6a55121965db0cc3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5570944$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5570944$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zhang, Gang</creatorcontrib><creatorcontrib>Ra, Chang Ho</creatorcontrib><creatorcontrib>Li, Hua-Min</creatorcontrib><creatorcontrib>Shen, Tian-zi</creatorcontrib><creatorcontrib>Cheong, Byung-ki</creatorcontrib><creatorcontrib>Yoo, Won Jong</creatorcontrib><title>Modified Potential Well Formed by \hbox/ \hbox/\hbox/\hbox for Flash Memory Application</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO 2 /SiO x ,Na-TiO x ,N y tunnel barrier, a trap-rich TiO 2 trapping layer, and an abrupt SiO 2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N 2 + O 2 thermal treatment, and the TiO 2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (<; μs) at low-voltage operation (7-10 MV/cm), good P/E endurance (> 10 6 P/E cycles), large threshold voltage window (ΔV th =M> V), as well as improved data retention at 125 °C.</description><subject>Electron traps</subject><subject>Flash memory</subject><subject>hbox{TiO}_{2} trapping layer</subject><subject>modified engineered-potential-well (MW)</subject><subject>Silicon</subject><subject>Tin</subject><subject>Transient analysis</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkEtLw0AUhQdRMFb3gpv5A2nvPJNZltqq0KKLSjdCmMyDjiSdMOnC_ntTGsTNOZzLPWfxIfRIYEoIqNl2-TylMCQKUlKAK5QRIYpcSS6vUQZAylyxkt2iu77_HqLknGZot4k2-OAs_ohHdzgG3eCdaxq8iqkdrvUJf-3r-DMb7Z9iHxNeNbrf441rYzrhedc1wehjiId7dON107uH0Sfoc7XcLl7z9fvL22K-zg2BkufWOKKZJowrD94KahQDAaUwRlrmCmmsLDUtqCoYr2XtpRaCUKKksDUYwyYILrsmxb5PzlddCq1Op4pAdQZTDWCqM5hqBDNUni6V4Jz7ex9YgeKc_QKMiF6V</recordid><startdate>201011</startdate><enddate>201011</enddate><creator>Zhang, Gang</creator><creator>Ra, Chang Ho</creator><creator>Li, Hua-Min</creator><creator>Shen, Tian-zi</creator><creator>Cheong, Byung-ki</creator><creator>Yoo, Won Jong</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>201011</creationdate><title>Modified Potential Well Formed by \hbox/ \hbox/\hbox/\hbox for Flash Memory Application</title><author>Zhang, Gang ; Ra, Chang Ho ; Li, Hua-Min ; Shen, Tian-zi ; Cheong, Byung-ki ; Yoo, Won Jong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1084-dce1a3a1349f0fd52c9305085cc6d3e76cd68a2729734b6bf6a55121965db0cc3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Electron traps</topic><topic>Flash memory</topic><topic>hbox{TiO}_{2} trapping layer</topic><topic>modified engineered-potential-well (MW)</topic><topic>Silicon</topic><topic>Tin</topic><topic>Transient analysis</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zhang, Gang</creatorcontrib><creatorcontrib>Ra, Chang Ho</creatorcontrib><creatorcontrib>Li, Hua-Min</creatorcontrib><creatorcontrib>Shen, Tian-zi</creatorcontrib><creatorcontrib>Cheong, Byung-ki</creatorcontrib><creatorcontrib>Yoo, Won Jong</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhang, Gang</au><au>Ra, Chang Ho</au><au>Li, Hua-Min</au><au>Shen, Tian-zi</au><au>Cheong, Byung-ki</au><au>Yoo, Won Jong</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Modified Potential Well Formed by \hbox/ \hbox/\hbox/\hbox for Flash Memory Application</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2010-11</date><risdate>2010</risdate><volume>57</volume><issue>11</issue><spage>2794</spage><epage>2800</epage><pages>2794-2800</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO 2 /SiO x ,Na-TiO x ,N y tunnel barrier, a trap-rich TiO 2 trapping layer, and an abrupt SiO 2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N 2 + O 2 thermal treatment, and the TiO 2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (<; μs) at low-voltage operation (7-10 MV/cm), good P/E endurance (> 10 6 P/E cycles), large threshold voltage window (ΔV th =M> V), as well as improved data retention at 125 °C.</abstract><pub>IEEE</pub><doi>10.1109/TED.2010.2066200</doi><tpages>7</tpages></addata></record> |
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| subjects | Electron traps Flash memory hbox{TiO}_{2} trapping layer modified engineered-potential-well (MW) Silicon Tin Transient analysis |
| title | Modified Potential Well Formed by \hbox/ \hbox/\hbox/\hbox for Flash Memory Application |
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