Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs
A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented. It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface...
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| Veröffentlicht in: | IEEE transactions on electron devices 2006-12, Vol.53 (12), p.3110-3117 |
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| container_end_page | 3117 |
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| container_issue | 12 |
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| container_title | IEEE transactions on electron devices |
| container_volume | 53 |
| creator | Chandrasekaran, K. Xing Zhou Siau Ben Chiah Guan Huei See Rustagi, S.C. |
| description | A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented. It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping. The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures, which exhibit confinement of carriers at the different interfaces |
| doi_str_mv | 10.1109/TED.2006.885520 |
| format | Article |
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It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping. The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures, which exhibit confinement of carriers at the different interfaces</description><subject>Applied sciences</subject><subject>Compact model</subject><subject>Compound structure devices</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>heterostructure MOSFET</subject><subject>Poisson solution</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>SiGe</subject><subject>strained silicon (s-Si)</subject><subject>surface potential</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpFkDtPwzAUhS0EEqUwM7BESIxp7fgRe6xKgUqtipSysESOYyNXaVJsZ-i_xyUVTPdxzj3S_QC4R3CCEBTT7eJ5kkHIJpxTmsELMEKU5qlghF2CEYSIpwJzfA1uvN_FkRGSjcDncn9orLIhmbWyOQarZJMUvTNS6emyDfq3S967oNtgT1rX9MF2rU9M55J1V-vGtl9JEZy0ra7TwibrTfGy2PpbcGVk4_XduY7BR1zP39LV5nU5n61ShREPqWQKi1wjxDFFpDYV1aLCpiYV1ooIYiqEc5xrgmjNDBcmE5WRGauk5Bgahcfgccg9uO671z6Uu6538RtfckYRFSIj0TQdTMp13jttyoOze-mOJYLliV8Z-ZUnfuXAL148nWOlj1CMk62y_v-MY0wo4dH3MPis1vpPJhEwzhj-ATJSeNM</recordid><startdate>20061201</startdate><enddate>20061201</enddate><creator>Chandrasekaran, K.</creator><creator>Xing Zhou</creator><creator>Siau Ben Chiah</creator><creator>Guan Huei See</creator><creator>Rustagi, S.C.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Optoelectronics. Solid state devices</topic><topic>SiGe</topic><topic>strained silicon (s-Si)</topic><topic>surface potential</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chandrasekaran, K.</creatorcontrib><creatorcontrib>Xing Zhou</creatorcontrib><creatorcontrib>Siau Ben Chiah</creatorcontrib><creatorcontrib>Guan Huei See</creatorcontrib><creatorcontrib>Rustagi, S.C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chandrasekaran, K.</au><au>Xing Zhou</au><au>Siau Ben Chiah</au><au>Guan Huei See</au><au>Rustagi, S.C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2006-12-01</date><risdate>2006</risdate><volume>53</volume><issue>12</issue><spage>3110</spage><epage>3117</epage><pages>3110-3117</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented. It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping. The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures, which exhibit confinement of carriers at the different interfaces</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2006.885520</doi><tpages>8</tpages></addata></record> |
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| ispartof | IEEE transactions on electron devices, 2006-12, Vol.53 (12), p.3110-3117 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Compact model Compound structure devices Electronics Exact sciences and technology heterostructure MOSFET Poisson solution Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SiGe strained silicon (s-Si) surface potential Transistors |
| title | Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs |
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