Hybrid Binary-Unary Hardware Accelerator

Stream-based computing such as stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the area saving comes at an exponential price in latency, making the area × delay cost unattractive. In this article, we...

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Veröffentlicht in:	IEEE transactions on computers 2020-09, Vol.69 (9), p.1308-1319
Hauptverfasser:	Faraji, S. Rasoul, Bazargan, Kia
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms alternator logic Application specific integrated circuits Computation Computer architecture CORDIC Delay Delays Edge detection Energy consumption Energy costs Field programmable gate arrays Hardware hardware accelerators Hybrid computing system Logic gates Methods Regression models Representations scaling network stochastic computing Stochastic processes Thermometers unary computing system
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