An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time
Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chi...
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Veröffentlicht in: | IEEE transactions on computers 2017-01, Vol.66 (1), p.38-44 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work. |
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ISSN: | 0018-9340 1557-9956 |
DOI: | 10.1109/TC.2016.2561920 |