Design and Analysis of Hybrid Flow Control for Hierarchical Ring Network-on-Chip

A cost-efficient network-on-chip is needed in a scalable many-core systems. Recent multicore processors have leveraged a ring topology and hierarchical ring can increase scalability but presents different challenges, including higher hop count and global ring bottleneck. In this work, we describe a...

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Veröffentlicht in:	IEEE transactions on computers 2016-02, Vol.65 (2), p.480-494
Hauptverfasser:	Hanjoon Kim, Gwangsun Kim, Hwasoo Yeo, Kim, John, Seungryoul Maeng
Format:	Artikel
Sprache:	eng
Schlagworte:	Buffers Channels Design analysis Ethernet Flow control Network topology Networks On-chip interconnection networks parallel architectures Ports (Computers) processor architectures Radiation detectors Rings (mathematics) Roads Routers Topology Vehicles
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